CS8900A-CQZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS8900A-CQZ Datasheet PDF : 138 Pages
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CS8900A
Crystal LAN™ Ethernet Controller
Status and Event Bits
Register
F
E
D
C
B
A
9
8
7
6 Number Name
(Offset)
Interrupt Status Queue
0
ISQ
(0120h)
Reserved (register contents undefined)
2
Extra Runt
data
CRC
error
Broad- Individ- Hashed RxOK Dribble IAHash 4
Rx
cast ual Adr
bits
(0124h) Event
Hash Table Index (alternate RxEvent meaning if
Hashed = 1 and RxOK = 1)
Hashed RxOK Dribble IAHash 4
Rx
bits
(0124h) Eventalt
Reserved (register contents undefined)
6
16coll
Number-of-Tx-collisions
Jabber Out-of- TxOK
Window
SQE Loss-of- 8 TxEvent
error CRS (0128h)
Reserved (register contents undefined)
A
Rx
Dest
Rx128 RxMiss TxUnder- Rdy4Tx RxDMA SWint
C
Buf
run
Frame
(012Ch) Event
Reserved (register contents undefined)
E
10-bit Receive Miss (RxMISS) counter, cleared when read
10 RxMISS
(0130h)
10-bit Transmit Collision (TxCOL) counter, cleared when read
12 TxCOL
(0132h)
CRS
Polarity
OK
10BT AUI LinkOK
14 LineST
(0134h)
EESize EL EEPRO EEPRO SIBUSY INITD 3.3 V
16 SelfST
present M OK Mpresent
Active (0136h)
Rdy4Tx TxBid
NOW Err
18 BusST
(0138h)
Reserved (register contents undefined)
1A
10-bit AUI Time Domain Reflectometer (TDR) counter, cleared when read
1C TDR
(013Ch)
Reserved (register contents undefined)
1E
Table 16. Status and Control Register Descriptions (continued)
4.4.5 Register 0: Interrupt Status Queue
(ISQ, Read-only, Address: PacketPage base + 0120h)
7
6
5
4
3
2
1
0
RegContent
RegNum
F
E
D
C
B
A
9
8
RegContent
The Interrupt Status Queue Register is used in both Memory Mode and I/O Mode to provide the host with interrupt
information. Whenever an event occurs that triggers an enabled interrupt, the CS8900A sets the appropriate bit(s)
in one of five registers, maps the contents of that register to the ISQ register, and drives an IRQ pin high. Three of
the registers mapped to ISQ are event registers: RxEvent (Register 4), TxEvent (Register 8), and BufEvent (Register
C). The other two registers are counter-overflow reports: RxMISS (Register 10) and TxCOL (Register 12). In Mem-
ory Mode, ISQ is located at PacketPage base + 120h. In I/O Mode, ISQ is located at I/O Base + 0008h. See
Section 5.1 on page 78.
CIRRUS LOGIC PRODUCT DATASHEET
DS271F4
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