CS8900A-CQZ View Datasheet(PDF) - Cirrus Logic
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CS8900A-CQZ Datasheet PDF : 138 Pages
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CS8900A
Crystal LAN™ Ethernet Controller
5.2.2.1 Configuring the Physical Interface
Configuring the physical interface consists of
determining which Ethernet interface should
be active, and enabling the receive logic for
serial reception. This is done via the LineCTL
register (Register 13) and is described in
Table19.
Register 13, LineCTL
Bit Bit Name
Operation
6 SerRxON When set, reception enabled.
8 AUIonly When set, AUI selected (takes
precedence over AutoAUI/10BT).
9 AutoAUI/10BT When set, automatic interface
selection enabled. When both bits
8 and 9 are clear, 10BASE-T
selected.
E LoRx Squelch When set, receiver squelch level
reduced by approximately 6 dB.
Table 19. Physical Interface Configuration
5.2.2.2 Choosing which Frame Types to Ac-
cept
The RxCTL register (Register 5) is used to de-
termine which frame types will be accepted by
the CS8900A (a receive frame is said to be
"accepted" when the frame is buffered, either
on chip or in host memory via DMA). Table 20
describes the configuration bits in this register.
Refer to Section 5.2.10 on page 87 for a de-
tailed description of Destination Address filter-
ing.
Register 5, RxCTL
Bit Bit Name
Operation
6 IAHashA When set, Individual Address frames
that pass the hash filter are
accepted*.
7 Promis When set, all frames are accepted*.
cuousA
8 RxOKA When set, frames with valid length
and CRC and that pass the DA filter
are accepted.
9 MulticastA When set, Multicast frames that pass
the hash filter are accepted*.
* Must also meet the criteria programmed into bits 8, C, D, and E.
Table 20. Frame Acceptance Criteria
Register 5, RxCTL
Bit Bit Name
Operation
A IndividualA When set, frames with DA that
matches the IA at PacketPage base
+ 0158h are accepted*.
B Broad- When set, all broadcast frames are
castA accepted*.
C CRCerrorA When set, frames with bad CRC that
pass the DA filter are accepted.
D RuntA When set, frames shorter than 64
bytes that pass the DA filter are
accepted.
E ExtradataA When set, frames longer than 1518
bytes that pass the DA filter are
accepted (only the first 1518 bytes
are buffered).
* Must also meet the criteria programmed into bits 8, C, D, and E.
Table 20. Frame Acceptance Criteria
5.2.2.3 Selecting which Events Cause Inter-
rupts
The RxCFG register (Register 3) and the
BufCFG register (Register B) are used to de-
termine which receive events will cause inter-
rupts to the host processor. Table 22
describes the interrupt enable (iE) bits in these
registers.
Register 3, RxCFG
Bit Bit Name
Operation
8 RxOKiE When set, there is an interrupt if a
frame is received with valid length
and CRC*.
C CRCerroriE When set, there is an interrupt if a
frame is received with bad CRC*.
D RuntiE When set, there is an interrupt if a
frame is received that is shorter than
64 bytes*.
E ExtradataiE When set, there is an interrupt if a
frame is received that is longer than
1518 bytes*.
* Must also pass the DA filter before there is an interrupt.
Table 21.
5.2.2.4 Choosing How to Transfer Frames
The RxCFG register (Register 3) and the Bus-
CTL register (Register 17) are used to deter-
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