M59MR032C, M59MR032D
Table 34. Program, Erase Times and Program, Erase Endurance Cycles
(TA = 0 to 70°C; VDD = VDDQ = 1.65V to 2.0V, VPP = VDD unless otherwise specified)
Parameter
Min
Max (1)
Typ
Typical after
100k W/E Cycles
Unit
Parameter Block (4 KWord) Erase (Preprogrammed)
2.5
0.15
0.4
sec
Main Block (32 KWord) Erase (Preprogrammed)
10
1
3
sec
Bank Erase (Preprogrammed, Bank A)
2
6
sec
Bank Erase (Preprogrammed, Bank B)
10
30
sec
Chip Program (2)
20
25
sec
Chip Program (DPG, VPP = 12V) (2)
10
sec
Word Program (3)
200
10
10
µs
Double Word Program
200
10
10
µs
Program/Erase Cycles (per Block)
100,000
cycles
Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or
erase should perform significantly better.
2. Excludes the time needed to execute the sequence for program instruction.
3. Same timing value if VPP = 12V.
Table 35. Data Polling and Toggle Bits AC Characteristics (1)
(TA = –40 to 85 °C; VDD = VDDQ = 1.65V to 2.0V)
Symbol
Parameter
Min
Chip Enable High to DQ7 Valid (Program, E Controlled)
10
tEHQ7V
Chip Enable High to DQ7 Valid (Block Erase, E Controlled)
1.0
Chip Enable High to Output Valid (Program)
10
tEHQV
Chip Enable High to Output Valid (Block Erase)
1.0
tQ7VQV
Q7 Valid to Output Valid (Data Polling)
Write Enable High to DQ7 Valid (Program, W Controlled)
10
tWHQ7V
Write Enable High to DQ7 Valid (Block Erase, W Controlled)
1.0
Write Enable High to Output Valid (Program)
10
tWHQV
Write Enable High to Output Valid (Block Erase)
1.0
Note: 1. All other timings are defined in Read AC Characteristics table.
Max
Unit
200
µs
10
sec
200
µs
10
sec
0
ns
200
µs
10
sec
200
µs
10
sec
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