QL5732-33BPS484M View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

Manufacturer

QL5732-33BPS484M

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5732 Enhanced QuickPCI Device Data Sheet Rev. E

Signal

Cfg_RdData[31:0]

Usr_RdData[31:0]

Cfg_CmdReg3

Cfg_CmdReg4

Cfg_CmdReg6

Cfg_CmdReg8

Cfg_LatCnt[7:0]

Usr_MstRdAd_Sel

Usr_MstWrAd_Sel

Cfg_PERR_Det

Cfg_SERR_Sig

Cfg_MstPERR_Det

Usr_TRDY

Usr_STOPO

Usr_DEVSEL

Usr_Last_Cycle_D1

Usr_Rdy

Usr_Stop

Usr_Abort

Table 2: PCI Target Interface

I/O

Description

I Data from the PCI configuration registers, required to be presented during PCI configuration

reads.

I Data from the back-end user logic required to be presented during PCI user reads.

I Bit 3 from the Command Register in the PCI configuration space (offset 04h). Enable Special

Cycle monitoring. If high, the core reports data parity error in Special Cycles through SERRN

if Cfg_CmdReg8 is active.

I Bit 4 from the Command Register in the PCI configuration space (offset 04h). Memory Write

and Invalidate (MWI) Enable. If high, the core generates MWI transactions as requested by the

backend. Otherwise it uses Memory Write instead even if MWI is requested.

I Bit 6 from the Command Register in the PCI configuration space (offset 04h). Parity Error

Response. If high, the core uses PERRN to report data parity errors. Otherwise it never drives

it.

I Bit 8 from the Command Register in the PCI configuration space (offset 04h). SERRN Enable.

If high, the cores uses SERRN to report address parity errors if Cfg_CmdReg6 is high.

I 8-bit value of the Latency Timer in the PCI configuration space (offset 0Ch).

I Used when a target Read operation should return the value set on the Mst_RdAd[31:0] pins.

This select pin saves on logic which would otherwise need to be used to multiplex

Mst_RdAd[31:0] into the Usr_RdData[31:0] bus. When this signal is asserted, the data on

Usr_RdData[31:0] is ignored.

I Used when a target read operation should return the value set on the Mst_WrAd[31:0] pins.

This select pin saves on logic which would otherwise need to be used to multiplex

Mst_WrAd[31:0] into the Usr_RdData[31:0] bus. When this signal is asserted, the data on

Usr_RdData[31:0] is ignored.

O Parity error detected on the PCI bus. When this signal is active, bit 15 of the Status Register

must be set in the PCI configuration space (offset 04h).

O System error asserted on the PCI bus. When this signal is active, the Signalled System Error

bit, bit 14 of the Status Register, must be set in the PCI configuration space (offset 04h).

O Data parity error detected on the PCI bus by the master. When this signal is active, bit 8 of the

Status Register must be set in the PCI configuration space (offset 04h).

O Inverted copy of the TRDYN signal as driven by the PCI target interface. Valid only within a

target access.

O Inverted copy of the STOPN signal as driven by the PCI target interface. Valid only within a

target access.

O Inverted copy of the DEVSELN signal as driven by the PCI target interface. Valid only within a

target access.

O Active one clock cycle after the last data phase (may not with data transfer) occurs on PCI and

inactive one clock cycle afterwards.

I Used to delay (add wait states to) a target PCI transaction when the backend needs additional

time to provide data (read) or accept data (write). Subject to PCI latency restrictions.

I Used to prematurely stop a PCI target access on the next PCI clock.

I Used to signal Target Abort on PCI when the backend has fatal errors and is unable to

complete a transaction. Rarely used.

© 2003 QuickLogic Corporation

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