D950CORE View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

D950CORE

16-Bit Fixed Point Digital Signal Processor (DSP) Core

STMicroelectronics 

D950-Core

7.3.2 I/O interface

In this section, the terms input and output are related to the interrupt controller, and the term

external is related to the AS-DSP.

The interrupt controller I/O interface signals are of two types:

On the D950-Core Side

• IT (maskable interrupt request / output)

• ITACK maskable interrupt request acknowledge / input)

• EOI (end of maskable interrupt routine / input)

• YA0/YA15 (Y address bus) and YD0/YD15 (Y data bus) with their associated

control signals:

YRD (read / input)

YWR (write / input)

• CLK clock / input

On the External Side

• ITRQ (7:0) (8 interrupt requests / inputs)

• RESET (reset / input)

7.3.3 Interrupt Controller Peripheral Registers

The interrupt controller interface is software controlled by thirteen status/control registers

mapped in the Y-memory space. Status registers are not protected against writing:

IVi: Interrupt Vector Register

One register is associated to each external interrupt.

IVi contains the first address of the interrupt routine associated to each ITRQi interrupt input

(with 0<i<7). The register content of the interrupt under service is assigned on the YD-bus

during the cycle following the ITACK falling edge where CLK=0.

After reset, IVi default value is 0.

IMR: Interrupt Mask Register

Each interrupt ITRQi can be masked individually when the IMi corresponding bit is set. In this

case, no activity on ITRQi is taken into account.

ITRQi can be activated on a low level or on a falling edge, according to associated ISi status.

When associated ISi-bit is reset (def. value), ITRQi must stay low for one period.

After reset, IMR default value is 0x5555.

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