DM9016
3-port switch with Processor Interface
5.10.2 Strap pin in 2-port mode
Pin No. Pin Name Description
50
EECK
Processor Data Bus Width
51
EEDO
EECK EEDO data width
0
0
16-bit (default)
0
1
32-bit
1
0
8-bit
1
1
(reserved)
52
EECS
Source of System Clock
0: system clock is internal 50MHz clock (default)
1: use SCLK pin as system clock
55
MDC
Polarity of IRQ
0: IRQ pin high active (default)
1: IRQ pin low active
58
TXD2_3 ISA pin control
0: GP6/5 as normal usage (default)
1: GP6 as IO16, GP5 as IOWAIT
59
TXD2_2 Port 2 force mode
0: Port 2 status from external PHY (N-way)
1: Port 2 in force mode
60
TXD2_1 Port 2 mode
61
TXD2_0 TXD2_1, TXD2_0
0
0 Port 2 is MII mode (default)
0
1 Port 2 is Reverse-MII mode
1
0 Port 2 is RMII mode
1
1 (reserved)
63
TXEN2
Disabled Port Selection
0: Port 2 is disabled (default)
1: Port 1 is disabled
115
GP2
Port 2 Force mode Speed is: (when TXD2_2 pulled high)
0: 100Mbps
1: 10Mbps
114
GP3
Port 2 Force mode Duplex is : (when TXD2_2 pulled high)
0: full-duplex
1: half-duplex
113
GP4
Port 2 Force mode Link is: (when TXD2_2 pulled high)
0: link
1: non-link
Preliminary datasheet
19
DM9016-13-DS-P01
March 26, 2009