DSPIC30F1013AT-30E/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC30F1013AT-30E/ML

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology 

dsPIC30F3014/4013

18.3.6 SLAVE FRAME SYNC OPERATION

When the DCI module is operating as a Frame Sync

slave (COFSD = 1), data transfers are controlled by the

Codec device attached to the DCI module. The

COFSM control bits control how the DCI module

responds to incoming COFS signals.

In the Multichannel mode, a new data frame transfer

begins one CSCK cycle after the COFS pin is sampled

high (see Figure 18-2). The pulse on the COFS pin

resets the Frame Sync generator logic.

In the I2S mode, a new data word is transferred one

CSCK cycle after a low-to-high or a high-to-low transi-

tion is sampled on the COFS pin. A rising or falling

edge on the COFS pin resets the Frame Sync

generator logic.

In the AC-Link mode, the tag slot and subsequent data

slots for the next frame is transferred one CSCK cycle

after the COFS pin is sampled high.

The COFSG and WS bits must be configured to

provide the proper frame length when the module is

operating in the Slave mode. Once a valid Frame Sync

pulse has been sampled by the module on the COFS

pin, an entire data frame transfer takes place. The

module will not respond to further Frame Sync pulses

until the data frame transfer has completed.

FIGURE 18-2:

FRAME SYNC TIMING, MULTICHANNEL MODE

CSCK

COFS

CSDI/CSDO

MSB

LSB

FIGURE 18-3:

FRAME SYNC TIMING, AC-LINK START-OF-FRAME

BIT_CLK

CSDO or CSDI

SYNC

S12 S12 S12 Tag Tag Tag

bit 2 bit 1 LSb MSb bit 14 bit 13

FIGURE 18-4:

I2S INTERFACE FRAME SYNC TIMING

CSCK

CSDI or CSDO

MSB

LSB MSB

LSB

WS

Note:

A 5-bit transfer is shown here for illustration purposes. The I2S protocol does not specify word length – this

will be system dependent.

DS70138E-page 118

© 2007 Microchip Technology Inc.

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