DSPIC30F5013CT-20I/PT View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC30F5013CT-20I/PT Datasheet PDF : 220 Pages
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dsPIC30F3014/4013
20.3 Oscillator Control Registers
The oscillators are controlled with two SFRs,
OSCCON and OSCTUN and one Configuration
register, FOSC.
Note:
The description of the OSCCON and
OSCTUN SFRs, as well as the FOSC Con-
figuration register provided in this section
are applicable only to the dsPIC30F3014
and dsPIC30F4013 devices in the
dsPIC30F product family.
REGISTER 20-1: OSCCON: OSCILLATOR CONTROL REGISTER
U-0
—
bit 15
R-y
R-y
R-y
COSC<2:0>
U-0
R/W-y
—
R/W-y
NOSC<2:0>
R/W-y
bit 8
R/W-0
R/W-0
POST<1:0>
bit 7
R-0
LOCK
U-0
R/W-0
—
CF
U-0
R/W-0
R/W-0
—
LPOSCEN OSWEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-12
bit 11
bit 10-8
bit 7-6
bit 5
Unimplemented: Read as ‘0’
COSC<2:0>: Current Oscillator Group Selection bits (Read-Only)
111 = PLL Oscillator; PLL source selected by FPR<4:0> bits
011 = External Oscillator; OSC1/OSC2 pins; External Oscillator configuration selected by FPR<4:0>
bits
010 = LPRC internal low-power RC
001 = FRC internal fast RC
000 = LP crystal oscillator; SOSCI/SOSCO pins
Set to FOS<2:0> values on POR or BOR
Loaded with NOSC<2:0> at the completion of a successful clock switch
Set to FRC value when FSCM detects a failure and switches clock to FRC
Unimplemented: Read as ‘0’
NOSC<2:0>: New Oscillator Group Selection bits
111 = PLL Oscillator; PLL source selected by FPR<4:0> bits
011 = External Oscillator; OSC1/OSC2 pins; External Oscillator configuration selected by FPR<4:0>
bits
010 = LPRC internal low-power RC
001 = FRC internal fast RC
000 = LP crystal oscillator; SOSCI/SOSCO pins
Set to FOS<2:0> values on POR or BOR
POST<1:0>: Oscillator Postscaler Selection bits
11 = Oscillator postscaler divides clock by 64
10 = Oscillator postscaler divides clock by 16
01 = Oscillator postscaler divides clock by 4
00 = Oscillator postscaler does not alter clock
LOCK: PLL Lock Status bit (Read-Only)
1 = Indicates that PLL is in lock
0 = Indicates that PLL is out of lock (or disabled)
Reset on POR or BOR
Reset when a valid clock switching sequence is initiated
Set when PLL lock is achieved after a PLL start
Reset when lock is lost
Read zero when PLL is not selected as a system clock
© 2007 Microchip Technology Inc.
DS70138E-page 141
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