DSPIC30F1013AT-30E/ML View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC30F1013AT-30E/ML Datasheet PDF : 220 Pages
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dsPIC30F3014/4013
D
Data Accumulators and Adder/Subtracter........................... 19
Data Accumulators and Adder/Subtractor
Data Space Write Saturation ...................................... 21
Overflow and Saturation ............................................. 19
Round Logic ................................................................ 20
Write-Back .................................................................. 20
Data Address Space ........................................................... 28
Alignment .................................................................... 31
Alignment (Figure) ...................................................... 31
Effect of Invalid Memory Accesses (Table)................. 31
MCU and DSP (MAC Class) Instructions Example..... 30
Memory Map ......................................................... 28, 29
Near Data Space ........................................................ 32
Software Stack ............................................................ 32
Spaces ........................................................................ 31
Width ........................................................................... 31
Data Converter Interface (DCI) Module ............................ 115
Data EEPROM Memory ...................................................... 47
Erasing ........................................................................ 48
Erasing, Block ............................................................. 48
Erasing, Word ............................................................. 48
Protection Against Spurious Write .............................. 50
Reading....................................................................... 47
Write Verify ................................................................. 50
Writing ......................................................................... 49
Writing, Block .............................................................. 49
Writing, Word .............................................................. 49
DC Characteristics ............................................................ 165
BOR .......................................................................... 173
Brown-out Reset ....................................................... 172
I/O Pin Input Specifications ....................................... 171
I/O Pin Output Specifications .................................... 171
Idle Current (IIDLE) .................................................... 168
Low-Voltage Detect................................................... 171
LVDL ......................................................................... 172
Operating Current (IDD)............................................. 167
Power-Down Current (IPD) ........................................ 169
Program and EEPROM............................................. 173
Temperature and Voltage Specifications .................. 165
DCI Module
Bit Clock Generator................................................... 119
Buffer Alignment with Data Frames .......................... 121
Buffer Control ............................................................ 115
Buffer Data Alignment ............................................... 115
Buffer Length Control ................................................ 121
COFS Pin .................................................................. 115
CSCK Pin .................................................................. 115
CSDI Pin ................................................................... 115
CSDO Mode Bit ........................................................ 122
CSDO Pin ................................................................. 115
Data Justification Control Bit ..................................... 120
Device Frequencies for Common Codec
CSCK Frequencies (Table)............................... 119
Digital Loopback Mode ............................................. 122
Enable ....................................................................... 117
Frame Sync Generator ............................................. 117
Frame Sync Mode Control Bits ................................. 117
I/O Pins ..................................................................... 115
Interrupts ................................................................... 122
Introduction ............................................................... 115
Master Frame Sync Operation .................................. 117
Operation .................................................................. 117
Operation During CPU Idle Mode ............................. 122
Operation During CPU Sleep Mode .......................... 122
DS70138E-page 210
Receive Slot Enable Bits .......................................... 120
Receive Status Bits................................................... 121
Register Map ............................................................ 124
Sample Clock Edge Control Bit ................................ 120
Slave Frame Sync Operation.................................... 118
Slot Enable Bits Operation with Frame Sync............ 120
Slot Status Bits ......................................................... 122
Synchronous Data Transfers .................................... 120
Timing Characteristics
AC-Link Mode................................................... 187
Multichannel, I2S Modes................................... 185
Timing Requirements
AC-Link Mode................................................... 188
Multichannel, I2S Modes................................... 185
Transmit Slot Enable Bits ......................................... 120
Transmit Status Bits.................................................. 121
Transmit/Receive Shift Register ............................... 115
Underflow Mode Control Bit...................................... 122
Word Size Selection Bits .......................................... 117
Development Support ....................................................... 161
Device Configuration
Register Map ............................................................ 152
Device Configuration Registers
FBORPOR ................................................................ 150
FGS .......................................................................... 150
FOSC........................................................................ 150
FWDT ....................................................................... 150
Device Overview................................................................... 9
Disabling the UART ............................................................ 99
Divide Support .................................................................... 16
Instructions (Table) ..................................................... 16
DSP Engine ........................................................................ 17
Multiplier ..................................................................... 19
Dual Output Compare Match Mode .................................... 82
Continuous Pulse Mode.............................................. 82
Single Pulse Mode...................................................... 82
E
Electrical Characteristics .................................................. 165
AC............................................................................. 174
DC ............................................................................ 165
Enabling and Setting Up UART
Alternate I/O ............................................................... 99
Setting Up Data, Parity and Stop Bit Selections ......... 99
Enabling the UART ............................................................. 99
Equations
ADC Conversion Clock ............................................. 127
Baud Rate................................................................. 101
Bit Clock Frequency.................................................. 119
COFSG Period.......................................................... 117
Serial Clock Rate ........................................................ 90
Time Quantum for Clock Generation ........................ 111
Errata .................................................................................... 7
Exception Sequence
Trap Sources .............................................................. 58
External Clock Timing Characteristics
Type A, B and C Timer ............................................. 181
External Clock Timing Requirements ............................... 175
Type A Timer ............................................................ 181
Type B Timer ............................................................ 182
Type C Timer ............................................................ 182
External Interrupt Requests ................................................ 60
F
Fast Context Saving ........................................................... 60
Flash Program Memory ...................................................... 41
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