DSPIC30F3013AT-20I/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC30F3013AT-20I/ML

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology 

dsPIC30F3014/4013

3.2 Data Address Space

The core has two data spaces. The data spaces can be

considered either separate (for some DSP instruc-

tions), or as one unified linear address range (for MCU

instructions). The data spaces are accessed using two

Address Generation Units (AGUs) and separate data

paths.

3.2.1 DATA SPACE MEMORY MAP

The data space memory is split into two blocks, X and

Y data space. A key element of this architecture is that

Y space is a subset of X space, and is fully contained

within X space. In order to provide an apparent Linear

Addressing space, X and Y spaces have contiguous

addresses.

When executing any instruction other than one of the

MAC class of instructions, the X block consists of the 64-

Kbyte data address space (including all Y addresses).

When executing one of the MAC class of instructions,

the X block consists of the 64-Kbyte data address

space excluding the Y address block (for data reads

only). In other words, all other instructions regard the

entire data memory as one composite address space.

The MAC class instructions extract the Y address space

from data space and address it using EAs sourced from

W10 and W11. The remaining X data space is

addressed using W8 and W9. Both address spaces are

concurrently accessed only with the MAC class

instructions.

The data space memory map is shown in Figure 3-7.

DS70138E-page 28

© 2007 Microchip Technology Inc.

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