DSPIC30F4013AT-20E/ML-ES View Datasheet(PDF) - Microchip Technology
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DSPIC30F4013AT-20E/ML-ES Datasheet PDF : 220 Pages
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9.5.1 RTC OSCILLATOR OPERATION
When the TON = 1, TCS = 1 and TGATE = 0, the timer
increments on the rising edge of the 32 kHz LP oscilla-
tor output signal, up to the value specified in the Period
register and is then reset to ‘0’.
The TSYNC bit must be asserted to a logic ‘0’
(Asynchronous mode) for correct operation.
Enabling LPOSCEN (OSCCON<1>) disables the nor-
mal Timer and Counter modes and enable a timer
carry-out wake-up event.
When the CPU enters Sleep mode, the RTC continues
to operate, provided the 32 kHz external crystal oscilla-
tor is active and the control bits have not been
changed. The TSIDL bit should be cleared to ‘0’ in
order for RTC to continue operation in Idle mode.
dsPIC30F3014/4013
9.5.2 RTC INTERRUPTS
When an interrupt event occurs, the respective interrupt
flag, T1IF, is asserted and an interrupt is generated, if
enabled. The T1IF bit must be cleared in software. The
respective Timer interrupt flag, T1IF, is located in the
IFS0 STATUS register in the interrupt controller.
Enabling an interrupt is accomplished via the respec-
tive timer interrupt enable bit, T1IE. The timer interrupt
enable bit is located in the IEC0 Control register in the
interrupt controller.
© 2007 Microchip Technology Inc.
DS70138E-page 65
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