dsPIC30F3014/4013
11.0 TIMER4/5 MODULE
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046).
This section describes the second 32-bit general
purpose Timer module (Timer4/5) and associated
operational modes. Figure 11-1 depicts the simplified
block diagram of the 32-bit Timer4/5 module.
Figure 11-2 and Figure 11-3 show Timer4/5 configured
as two independent 16-bit timers, Timer4 and Timer5,
respectively.
The Timer4/5 module is similar in operation to the
Timer2/3 module. However, there are some
differences which are listed:
• The Timer4/5 module does not support the ADC
event trigger feature
• Timer4/5 can not be utilized by other peripheral
modules, such as input capture and output compare
The operating modes of the Timer4/5 module are deter-
mined by setting the appropriate bit(s) in the 16-bit
T4CON and T5CON SFRs.
For 32-bit timer/counter operation, Timer4 is the lsw
and Timer5 is the msw of the 32-bit timer.
Note:
For 32-bit timer operation, T5CON control
bits are ignored. Only T4CON control bits
are used for setup and control. Timer4
clock and gate inputs are utilized for the
32-bit timer module but an interrupt is
generated with the Timer5 interrupt flag
(T5IF) and the interrupt is enabled with the
Timer5 interrupt enable bit (T5IE).
FIGURE 11-1:
32-BIT TIMER4/5 BLOCK DIAGRAM
Data Bus<15:0>
Write TMR4
Read TMR4
TMR5HLD
16
16
16
Reset
TMR5
MSB
TMR4
LSB
Equal
Comparator x 32
Sync
0
T5IF
Event Flag 1
TGATE
(T4CON<6>)
PR5
PR4
QD
Q CK
TGATE (T4CON<6>)
T4CK
Gate
Sync
TCY
TON
1x
01
00
TCKPS<1:0>
2
Prescaler
1, 8, 64, 256
Note:
Timer Configuration bit T32 (T4CON<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control
bits are respective to the T4CON register.
© 2007 Microchip Technology Inc.
DS70138E-page 73