DSPIC30F4013AT-20E/ML-ES View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC30F4013AT-20E/ML-ES

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology 

dsPIC30F3014/4013

12.0 INPUT CAPTURE MODULE

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

This section describes the input capture module and

associated operational modes. The features provided

by this module are useful in applications requiring fre-

quency (period) and pulse measurement. Figure 12-1

depicts a block diagram of the input capture module.

Input capture is useful for such modes as:

• Frequency/Period/Pulse Measurements

• Additional Sources of External Interrupts

The key operational features of the input capture

module are:

• Simple Capture Event mode

• Timer2 and Timer3 mode selection

• Interrupt on input capture event

These operating modes are determined by setting the

appropriate bits in the ICxCON register (where

x = 1,2,...,N). The dsPIC DSC devices contain up to 8

capture channels (i.e., the maximum value of N is 8).

The dsPIC30F3014 device contains 2 capture

channels while the dsPIC30F4013 device contains 4

capture channels.

12.1 Simple Capture Event Mode

The simple capture events in the dsPIC30F product

family are:

• Capture every falling edge

• Capture every rising edge

• Capture every 4th rising edge

• Capture every 16th rising edge

• Capture every rising and falling edge

These simple Input Capture modes are configured by

setting the appropriate bits, ICM<2:0> (ICxCON<2:0>).

12.1.1 CAPTURE PRESCALER

There are four input capture prescaler settings speci-

fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the

capture channel is turned off, the prescaler counter is

cleared. In addition, any Reset clears the prescaler

counter.

FIGURE 12-1:

INPUT CAPTURE MODE BLOCK DIAGRAM

From GP Timer Module

T2_CNT T3_CNT

ICx pin

Prescaler

1, 4, 16

Clock

Synchronizer

3

ICM<2:0>

Mode Select

ICBNE, ICOV

Edge

Detection

Logic

ICxCON

ICI<1:0>

Interrupt

Logic

FIFO

R/W

Logic

16 16

ICTMR

10

ICxBUF

Note:

Data Bus

Set Flag

ICxIF

Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture

channels 1 through N.

© 2007 Microchip Technology Inc.

DS70138E-page 77

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