DSPIC30F0013AT-30E/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

DSPIC30F0013AT-30E/ML

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology 

dsPIC30F3014/4013

13.0 OUTPUT COMPARE MODULE

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

This section describes the output compare module and

associated operational modes. The features provided

by this module are useful in applications requiring

operational modes, such as:

• Generation of Variable Width Output Pulses

• Power Factor Correction

Figure 13-1 depicts a block diagram of the output

compare module.

The key operational features of the output compare

module include:

• Timer2 and Timer3 Selection mode

• Simple Output Compare Match mode

• Dual Output Compare Match mode

• Simple PWM mode

• Output Compare During Sleep and Idle modes

• Interrupt on Output Compare/PWM Event

These operating modes are determined by setting the

appropriate bits in the 16-bit OCxCON SFR (where

x = 1,2,3,...,N). The dsPIC DSC devices contain up to

8 compare channels (i.e., the maximum value of N is 8).

The dsPIC30F3014 device contains 2 compare

channels while the dsPIC30F4013 device contains 4

compare channels.

OCxRS and OCxR in Figure 13-1 represent the Dual

Compare registers. In the Dual Compare mode, the

OCxR register is used for the first compare and OCxRS

is used for the second compare.

13.1 Timer2 and Timer3 Selection Mode

Each output compare channel can select between one

of two 16-bit timers, Timer2 or Timer3.

The selection of the timers is controlled by the OCTSEL

bit (OCxCON<3>). Timer2 is the default timer resource

for the output compare module.

FIGURE 13-1:

OUTPUT COMPARE MODE BLOCK DIAGRAM

Set Flag bit

OCxIF

OCxRS

OCxR

Comparator

OCTSEL

0

1

0

Output

Logic

3

OCM<2:0>

Mode Select

1

From GP

Timer Module

TMR2<15:0

TMR3<15:0> T2P2_MATCH T3P3_MATCH

SQ

R

Output OCx

Enable

OCFA

(for x = 1, 2, 3 or 4)

or OCFB

(for x = 5, 6, 7 or 8)

Note:

Where ‘x’ is shown, reference is made to the registers associated with the respective output compare

channels 1 through N.

© 2007 Microchip Technology Inc.

DS70138E-page 81

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