RC28F256J3C-125 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

RC28F256J3C-125

Intel StrataFlash® Memory (J3)

Intel 

256-Mbit J3 (x8/x16)

7.4

Reset Operation

Figure 14. AC Waveform for Reset Operation

VIH

STS (R)

VIL

P2

RP# (P) VIH

VIL

P1

NOTE: STS is shown in its default mode (RY/BY#).

Table 11. Reset Specifications

# Sym

Parameter

Min Max Unit Notes

RP# Pulse Low Time

P1 tPLPH (If RP# is tied to VCC, this specification is not

35

applicable)

µs

1,2

P2 tPHRH

RP# High to Reset during Block Erase, Program, or

Lock-Bit Configuration

100

ns

1,3

NOTES:

1. These specifications are valid for all product versions (packages and speeds).

2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not

executing then the minimum required RP# Pulse Low Time is 100 ns.

3. A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until

outputs are valid.

7.5

AC Test Conditions

Figure 15. Transient Input/Output Reference Waveform for VCCQ = 2.7 V–3.6 V

VCCQ

Input VCCQ/2

0.0

Test Points

VCCQ/2 Output

NOTE: AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and

output timing ends, at VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.

Datasheet

29

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