JS28F256J3A-125 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

JS28F256J3A-125

Intel StrataFlash® Memory (J3)

Intel 

256-Mbit J3 (x8/x16)

Table 22. STS Configuration Coding Definitions

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

Pulse on

Program

Complete

(1)

Pulse on

Erase

Complete

(1)

D[1:0] = STS Configuration Codes

Notes

10 = pulse on Program Complete

Used to generate a system interrupt pulse when any flash device in

an array has completed a program operation. Provides highest

performance for servicing continuous buffer write operations.

11 = pulse on Erase or Program

Complete

Used to generate system interrupts to trigger servicing of flash arrays

when either erase or program operations are completed, when a

common interrupt service routine is desired.

NOTES:

1. When configured in one of the pulse modes, STS pulses low with a typical pulse width of 250 ns.

2. An invalid configuration code will result in both SR.4 and SR.5 being set.

Datasheet

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