RC28F256J3C-150 View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
RC28F256J3C-150 Datasheet PDF : 72 Pages
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Figure 20. Byte/Word Program Flowchart
256-Mbit J3 (x8/x16)
Start
Write 40H,
Address
Write Data and
Address
Read Status
Register
SR.7 =
0
1
Full Status
Check if Desired
Byte/Word
Program Complete
FULL STATUS CHECK PROCEDURE
Read Status
Register Data
(See Above)
SR.3 =
1
Voltage Range Error
0
SR.1 =
1
Device Protect Error
0
1
SR.4 =
Programming Error
0
Byte/Word
Program
Successful
Bus
Operation
Write
Write
Read
(Note 1)
Standby
Command
Comments
Setup Byte/ Data = 40H
Word Program Addr = Location to Be Programmed
Byte/Word
Program
Data = Data to Be Programmed
Addr = Location to Be Programmed
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
1. Toggling OE# (low to high to low) updates the status register. This
can be done in place of issuing the Read Status Register command.
Repeat for subsequent programming operations.
SR full status check can be done after each program operation, or
after a sequence of programming operations.
Write FFH after the last program operation to place device in read
array mode.
Bus
Operation
Command
Comments
Standby
Check SR.3
1 = Programming to Voltage Error
Detect
Standby
Check SR.1
1 = Device Protect Detect
RP# = V IH, Block Lock-Bit Is Set
Only required for systems
implemeting lock-bit configuration.
Standby
Check SR.4
1 = Programming Error
Toggling OE# (low to high to low) updates the status register. This can
be done in place of issuing the Read Status Register command.
Repeat for subsequent programming operations.
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are programmed before
full status is checked.
If an error is detected, clear the status register before attempting retry
or other error recovery.
Datasheet
61
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