Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
PIN Description
Ball Name
Ball Location
Description
VOUT_CH[0:3]_[0:4]
G13, G15, F14, F13, F15, G3, F1, F2, Group A DAC output volages for channels 0 to 3.
F3, E1, J3, J1, K2, K3, K1, J13, K15,
K14, K13, L15
VOUT_CH[0:3]_[5:6] E14, E15, E2, E3, L2, L1, L14, L13 Group B DAC output voltages for channels 0 to 3.
VOUT_CH[0:3]_[7:8] E13, D14, D1, D2, L3, M2, M15, M14 Group C DAC output voltaqges for channels 0 to 3.
VOUT_CH[0:3]_[9:10] D15, D13, D3, C1, M1, M3, M13, N15 Group D DAC output voltages for channels 0 to 3.
IOUT_CH[0:3]_[0:1] C15, C14, B1, C2, N1, N2, P15, N14 Group E DAC output voltages for channels 0 to 3.
IOUT_CH[0:3]_[2:4] H14, H15, G14, H3, G1, G2, H2, H1, Group F DAC output voltages for channels 0 to 3.
J2, H13, J15, J14
R_MASTER
P5
Master external resistor used to define the reference current
for the gain and offset setting block for voltage DACs.
R_GAIN_(A,B,C,D,E,F)
P11, R10, N10, P10, R9, N9
Pins for external resistor to set current gain for both voltage
and current output DACs.
R_OFFSET_(A,B,C,D)
R6, P6, N6, R5
Pins for external resistor to set the offset voltage for Group
A, B, C, and D voltage output DAC's.
SDI
B10
Serial data input.
CK
A11
Clock for the input data shift register.
UPDATE
C6
Strobe to transfer the shift register data to the DACs.
CE
A10
Chip enable.
RESET*
C5
Active low chip reset. Sets the DACs to a known default
state.
SDO
B5
Serial Data Out.
CK_OUT
A6
Regenerated clock output for daisy chain purposes.
SCAN_OUT
B11
Analog output test pin.
TEST_MODE
B6
Test mode pin for internal scan.
VREF
C9
Reference input (for a 2.5V band gap).
AVCC
C3, C12, N4, R12
Positive analog voltage supply.
AVDD
C7, N7
Analog 5V supply.
VEE
A9, R8, B9, P9
Negative analog voltage supply.
AGND
B8, N8
Analog ground (minimize noise).
SGND
A8, R7
Supply ground.
DVDD
B7, P7
Digital voltage supply.
DGND
2000 Semtech Corp.
C8, P8
Digital supply ground.
2
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