FDC37B72X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37B72X

128 Pin Enhanced Super I/O Controller with ACPI Support

SMSC -> Microchip 

An overrun or underrun will terminate the current

command and the transfer of data. Disk writes will

complete the current sector by generating a 00

pattern and valid CRC. Reads require the host to

remove the remaining data so that the result

phase may be entered.

TABLE 15 - FIFO SERVICE DELAY

FIFO THRESHOLD

MAXIMUM DELAY TO SERVICING AT

EXAMPLES

2 Mbps DATA RATE

1 byte

1 x 4 μs - 1.5 μs = 2.5 μs

2 bytes

8 bytes

15 bytes

2 x 4 μs - 1.5 μs = 6.5 μs

8 x 4 μs - 1.5 μs = 30.5 μs

15 x 4 μs - 1.5 μs = 58.5 μs

FIFO THRESHOLD

EXAMPLES

1 byte

2 bytes

8 bytes

15 bytes

MAXIMUM DELAY TO SERVICING AT

1 Mbps DATA RATE

1 x 8 μs - 1.5 μs = 6.5 μs

2 x 8 μs - 1.5 μs = 14.5 μs

8 x 8 μs - 1.5 μs = 62.5 μs

15 x 8 μs - 1.5 μs = 118.5 μs

FIFO THRESHOLD

EXAMPLES

1 byte

2 bytes

8 bytes

15 bytes

MAXIMUM DELAY TO SERVICING AT

500 Kbps DATA RATE

1 x 16 μs - 1.5 μs = 14.5 μs

2 x 16 μs - 1.5 μs = 30.5 μs

8 x 16 μs - 1.5 μs = 126.5 μs

15 x 16 μs - 1.5 μs = 238.5 μs

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