GAL20V8C-7LP View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
GAL20V8C-7LP Datasheet PDF : 23 Pages
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Power-Up Reset
Specifications GAL20V8
Vcc (min.)
Vcc
CLK
tpr
INTERNAL REGISTER
Q - OUTPUT
tsu
t wl
Internal Register
Reset to Logic "0"
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
Circuitry within the GAL20V8 provides a reset signal to all registers
during power-up. All internal registers will have their Q outputs set
low after a specified time (tpr, 1µs MAX). As a result, the state on
the registered output pins (if they are enabled) will always be high
on power-up, regardless of the programmed polarity of the output
pins. This feature can greatly simplify state machine design by pro-
viding a known state on power-up. Because of the asynchronous
nature of system power-up, some conditions must be met to provide
a valid power-up reset of the device. First, the VCC rise must be
monotonic. Second, the clock input must be at static TTL level as
shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation, avoid
clocking the device until all input and feedback path setup times
have been met. The clock must also meet the minimum pulse width
requirements.
Input/Output Equivalent Schematics
PIN
Vcc
Active Pull-up
Circuit
Vcc Vref Vcc
ESD
Protection
Circuit
PIN
PIN
Feedback
Tri-State
Control
Active Pull-up
Circuit
Vcc
Vref
Data
Output
PIN
ESD
Protection
Circuit
Typ. Vref = 3.2V
Typical Input
Typ. Vref = 3.2V
Feedback
(To Input Buffer)
Typical Output
17
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