ISL9305IRTHWCNLZ-T(2010) View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

ISL9305IRTHWCNLZ-T
(Rev.:2010)

3MHz Dual 1.5A Step-Down Converters and Dual Low-Input LDOs with I2C Compatible Interface

Intersil 

ISL9305H

DCD1 AND DCD2 CONTROL REGISTER

DCD_PARAMETER, address 0x04h

TABLE 6. DCD_PARAMETER REGISTER

BIT NAME ACCESS RESET

DESCRIPTION

B7

-

-

0

Reserved

B6 DCD_PHASE R/W

0 DCD1 and DCD2 PWM switch

selection. 0-in phase; 1 to 180°

out-of-phase.

B5 DCD2_ULTRA R/W

B4 DCD1_ULTRA R/W

B3 DCD2_BLD R/W

0 Ultrasonic feature under PFM mode

for DCD2. 0-disabled; 1-enabled.

0 Ultrasonic feature under PFM mode

for DCD1. 0-disabled; 1-enabled.

1 Selection of DCD2 for active output

voltage discharge when disabled.

0-disabled; 1-enabled.

B2 DCD1_BLD R/W

1 Selection of DCD1 for active output

voltage discharge when disabled.

0-disabled; 1-enabled.

B1 DCD2_MODE R/W

B0 DCD1_MODE R/W

1 Selection on DCD2 of auto

PFM/PWM mode (= 1) or forced

PWM mode (= 0).

1 Selection on DCD1 of auto

PFM/PWM mode (= 1) or forced

PWM mode (= 0).

DCD OUTPUT VOLTAGE SLEW RATE CONTROL

REGISTER

DCD_SRCTL, address 0x06h

TABLE 8. DCD OUPUT VOLTAGE SLEW RATE CONTROL

REGISTER

BIT NAME ACCESS RESET

DESCRIPTION

B7 DCD2SR_2 R/W

B6 DCD2SR_1 R/W

B5 DCD2SR_0 R/W

0 DCD2 Slew Rate Setting, DCD2SR[2:0]:

000 to 0.225mV/µs

0 001 to 0.45mV/µs

1 010 to 0.90mV/µs

011 to 1.8mV/µs

100 to 3.6mV/µs

101 to 7.2mV/µs

110 to 14.4mV/µs

111 to immediate

B4 Reserve

-

0 Reserved

B3 DCD1SR_2 R/W

B2 DCD1SR_1 R/W

B1 DCD1SR_0 R/W

0 DCD1 Slew Rate Setting, DCD1SR[2:0]:

000 to 0.225mV/µs

0 001 to 0.45mV/µs

1 010 to 0.90mV/µs

011 to 1.8mV/µs

100 to 3.6mV/µs

101 to 7.2mV/µs

110 to 14.4mV/µs

111 to immediate

B0 Reserve

-

0 Reserved

SYSTEM CONTROL REGISTER

SYS_PARAMETER, address 0x05h

TABLE 7. SYS_PARAMETER REGISTER

BIT NAME ACCESS RESET

DESCRIPTION

B7

-

B6 I2C_EN

-

R/W

0 Reserved

0 I2C function enable. 0-disabled;

1-enabled

B5 DCDPOR_1 R/W

B4 DCDPOR_0 R/W

1 DCDPG Delay Time Setting,

DCDPG[1:0]:

0 00 to 1ms

01 to 50ms

10 to 150ms

11 to 200m

B3 LDO2_EN R/W

1 LDO2 enable selection. 0-disable,

1-enable.

B2 LDO1_EN R/W

1 LDO1 enable selection. 0-disable,

1-enable

B1 DCD2_EN R/W

1 DCD2 enable selection. 0-disable,

1-enable.

B0 DCD1_EN R/W

1 DCD2 enable selection. 0-disable,

1-enable

12

FN7724.0

November 8, 2010

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