ISL9305IRTHWCNYZ-T(2010) View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

ISL9305IRTHWCNYZ-T
(Rev.:2010)

3MHz Dual 1.5A Step-Down Converters and Dual Low-Input LDOs with I2C Compatible Interface

Intersil 

ISL9305H

PARTS DESCRIPTION

L1, L2 Inductor

C1 Input capacitor

C2, C3 Intput capacitor

C4, C5 Output capacitor

C6, C7 Output capacitor

R1, R2, Resistor

R3, R4

TABLE 1. TYPICAL APPLICATION PART LIST

MANUFACTURER

PART NUMBER

SPECIFICATIONS

Sumida

CDRH2D14NP-1R5

1.5µH/1.80A/50mΩ

Murata

GRM21BR60J106KE19L 10µF/6.3V

Murata

GRM185R60J105KE26D 1µF/6.3V

Murata

GRM21BR71A106KE51L 10µF/6.3V

Murata

GRM185R60J105KE26D 1µF/6.3V

Various

1%, SMD, 0.1W

SIZE

3.0mmx3.0mmx1.55mm

0805

0603

0805

0603

0603

Pin Configuration

ISL9305H

(16 LD 4X4 TQFN)

TOP VIEW

16 15 14 13

VINDCD1 1

12 VINDCD2

FB1 2

SCLK 3

SDAT 4

5

E-PAD

6

7

11 FB2

10 DCDPG

9 GNDLDO

8

Pin Descriptions

PIN NUMBER

(TQFN)

1

2

3

4

5

6

7

8

9

10

NAME

VINDCD1

FB1

SCLK

SDAT

VINLDO1

VOLDO1

VOLDO2

VINLDO2

GNDLDO

DCDPG

DESCRIPTION

Input voltage for buck converter DCD1 and it also serves as the power supply pin for the whole internal digital/analog

circuits.

Feedback pin for DCD1, connect external voltage divider resistors between DCDC1 output, this pin and ground. For

fixed output versions, connect this pin directly to the DCD1 output.

I2C interface clock pin.

I2C interface data pin.

Input voltage for LDO1.

Output voltage of LDO1.

Output voltage of LDO2.

Input voltage for LDO2.

Power ground for LDO1 and LDO2.

The DCDPG pin is an open-drain output to indicate the state of the DCD1/DCD2 output voltages. When both DCD1

and DCD2 are enabled, the output is released to be pulled high by an external pull-up resistor if both converter

voltages are within the power good range. The pin will be pulled low if either DCD is outside their range. When only

one DCD is enabled, the state of the enabled DCD’s output will define the state of the DCDPG pin. The DCDPG state

can be programmed for a delay of up to 200ms before being released to rise high. The programming range is

1ms~200ms through the I2C interface.

2

FN7724.0

November 8, 2010

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