ISL9305IRTHWCNLZ-T(2010) View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

ISL9305IRTHWCNLZ-T
(Rev.:2010)

3MHz Dual 1.5A Step-Down Converters and Dual Low-Input LDOs with I2C Compatible Interface

Intersil 

ISL9305H

Electrical Specifications

Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the

typical specifications are measured at the following conditions: TA = +25°C, VINDCD1 = 3.6V, VINDCD2 = 3.3V. For

LDO1 and LDO2, VINLDOx = VOLDOx + 0.5V to 5.5V with VINLDOx always no higher than VINDCD1, L1 = L2 = 1.5µH,

C1 = 10µF, C4 = C5 = 10µF, C2 = C3 = C6 = C7 = 1µF, IOUT = 0A for DCD1, DCD2, LDO1 and LDO2 (see “TYPICAL

APPLICATION DIAGRAM” on page 1 for more details). (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

MAX

(Note 6) TYP (Note 6) UNIT

Maximum Output Current

1500 -

-

mA

P-Channel MOSFET ON-resistance

N-Channel MOSFET ON-resistance

P-Channel MOSFET Peak Current Limit

SW Maximum Duty Cycle

VIN = 3.6V, IO = 200mA

VIN = 2.3V, IO = 200mA

VIN = 3.6V, IO = 200mA

VIN = 2.3V, IO = 200mA

IPK

-

0.14 0.20

Ω

-

0.24 0.40

Ω

-

0.11 0.20

Ω

0.18 0.34

Ω

2.1 2.5 2.75

A

-

100

-

%

SW Leakage Current

PWM Switching Frequency

SW Minimum ON-time

Bleeding Resistor

VIN = 5.5V

fS

VFB = 0.75V

- 0.005 1

µA

2.6 3.0 3.4 MHz

-

70

-

ns

-

115

-

Ω

PG

Output Low Voltage

Sinking 1mA, FB1 = FB2 = 0.7V

-

-

0.25

V

Rising Delay Time

Based on 1ms programmed nominal delay time

0.6 1.1 1.8 ms

Falling Delay Time

Based on 1ms programmed nominal delay time

-

30

-

µs

PG Pin Leakage Current

PG = VINDCD1 = VINDCD2 = 3.6V

- 0.005 0.1

µA

PG Low Rising Threshold

Percentage of nominal regulation voltage

-

91

-

%

PG Low Falling Threshold

Percentage of nominal regulation voltage

-

87

-

%

PG High Rising Threshold

Percentage of nominal regulation voltage

-

112

-

%

PG High Falling Threshold

Percentage of nominal regulation voltage

-

109

-

%

LDO1 AND LDO2

VINLDO1, VINLDO2 Supply Voltage

No higher than VINDCD1

1.5

-

5.5

V

VINLDO1, VINLDO2 Undervoltage

Lockout Threshold

VUVLO

Rising

Falling

-

1.41 1.46

V

1.33 1.37

-

V

Internal Peak Current Limit

350 425 540 mA

Dropout Voltage

IO = 300mA, VO ≤ 2.1V

-

IO = 300mA, 2.1V < VO ≤ 2.8V

-

IO = 300mA, VO > 2.8V

-

Power Supply Rejection Ratio

IO = 300mA @ 1kHz, VIN = 3.6V, VO = 2.6V, TA = +25°C

-

Output Voltage Noise

VIN = 4.2V, IO = 10mA, TA = +25°C, BW = 10Hz to 100kHz -

NOTE:

6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

120 250 mV

100 200 mV

80 170 mV

55

-

dB

45

-

µVRMS

6

FN7724.0

November 8, 2010

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