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LX256B-5FN208C View Datasheet(PDF) - Lattice Semiconductor

Part Name
Description
Manufacturer
LX256B-5FN208C
Lattice
Lattice Semiconductor 
LX256B-5FN208C Datasheet PDF : 72 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
Lattice Semiconductor
ispGDX2 Family Data Sheet
sysIO Single Ended DC Electrical Characteristics
Over Recommended Operating Conditions
Input/Output
Standard
VIL
Min (V)
Max (V)
VIH
Min (V)
Max (V)
VOL
Max (V)
VOH
Min (V)
IOL2
(mA)
IOH2
(mA)
LVCMOS 3.3
-0.3
0.8
2.0
5.5
0.4
2.4
20, 16, 12, -20, -16, -12,
8, 5.33, 4 -8, -5.33, -4
0.2
VCCO - 0.2
0.1
-0.1
LVTTL
0.4
2.4
4
-4
-0.3
0.8
2.0
5.5
0.2
VCCO - 0.2
0.1
-0.1
LVCMOS 2.5
-0.3
0.7
1.7
3.6
0.4
VCCO - 0.4
16, 12, 8,
5.33, 4
-16, -12, -8,
-5.33, -4
0.2
VCCO - 0.2
0.1
-0.1
LVCMOS 1.81, 3
-0.3
0.68
1.07
3.6
0.4
VCCO - 0.4
8
-8
LVCMOS 1.83
-0.3
0.68
1.07
3.6
0.4
VCCO -0.4 12, 5.33, 4 -12, -5.33, -4
0.2
VCCO - 0.2
0.1
-0.1
PCI 3.34
-0.3
1.08
1.5
3.6
0.1 VCCO 0.9 VCCO
1.5
-0.5
PCI -X5
-0.3
1.26
1.5
3.6
0.1 VCCO 0.9 VCCO
1.5
-0.5
AGP-1X4
-0.3
1.08
1.5
3.6
0.1 VCCO 0.9 VCCO
1.5
-0.5
SSTL3 class I
-0.3
VREF - 0.2 VREF + 0.2
3.6
0.7
VCCO - 1.1
8
-8
SSTL3 class II
-0.3
VREF - 0.2 VREF + 0.2
3.6
0.5
VCCO - 0.9
16
-16
SSTL2 class I
-0.3
VREF - 0.18 VREF + 0.18
3.6
0.54
VCCO - 0.62
7.6
-7.6
SSTL2 class II
-0.3
VREF - 0.18 VREF + 0.18
3.6
0.35
VCCO - 0.43
15.2
-15.2
CTT 3.3
-0.3
VREF - 0.2 VREF + 0.2
3.6
VREF - 0.4 VREF + 0.4
8
-8
CTT 2.5
-0.3
VREF - 0.3 VREF + 0.2
3.6
VREF - 0.4 VREF + 0.4
8
-8
HSTL class I
-0.3
VREF - 0.1 VREF + 0.1
3.6
0.4
VCCO - 0.4
8
-8
HSTL class III
-0.3
VREF - 0.2 VREF + 0.1
3.6
0.4
VCCO - 0.4
24
-8
HSTL class IV
-0.3
VREF - 0.3 VREF + 0.1
3.6
0.4
VCCO - 0.4
48
-8
GTL+
-0.3
VREF - 0.2 VREF + 0.2
3.6
0.6
n/a
36
n/a
1. Software default setting.
2. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of
the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND
connections or between the last GND in a bank and the end of a bank.
3. For 1.8V devices (ispGDX2C) these specifications are VIL = 0.35 VCC and VIH = 0.65VCC
4. For 1.8V power supply devices these specifications are VIL = 0.3 * VCC * 3.3/1.8, VIH = 0.5 * VCC * 3.3/1.8
5. For 1.8V power supply devices these specifications are VIL = 0.35 * VCC * 3.3/1.8 and VIH = 0.5 * VCC * 3.3/1.8
25

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