LX64C-5FN100C View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

LX64C-5FN100C

High Performance Interfacing and Switching

Lattice Semiconductor 

Lattice Semiconductor

ispGDX2 Family Data Sheet

Figure 19. ispGDX2 Timing Model Diagram (with sysHSI and FIFO Receive Mode)

to I/O Cell

(RECCLK)

from I/O Cell

(SIN)

tHSISIN

from I/O Cell

(Control)

tHSICTRLCAL

from I/O Cell

(SSCLKIN)

from I/O Cell

(REFCLK)

tHSISSCLKIN

tHSIREFCLK

sysHSI

(RXD)

Serial Data

In

Data Out

(RXD)

tFIFODATAIN

HSI Controls

Recovered

Clock

tFIFOWCLK

CAL

Source

Synchronous Clock

Reference Clock

RESET

HSI Flags

CSLOCK

SYDT

to I/O Cell

(Output Path Flag)

to I/O Cell

(SYDT and Output

Path Flags)

from I/O Cell

(RCLK)

from I/O Cell

(RE)

tFIFORCLK

tFIFOREN

Data In

FIFO

Write CLK

Data Out

Read

Clock

Read

Enable

FIFO Flags

FULL, EMPTY

RESET

to I/O Cell

(DOUT)

to I/O Cell

(Output Path Flags)

from I/O Cell

(Global RESET)

from I/O Cell

(I/O RESET)

tHSIFIFORST

Figure 20. ispGDX2 Timing Model Diagram (with sysHSI Transmit Mode)

from I/O Cell

(TXD)

tHSITXDATA

Data In

sysHSI

(TXD)

Serial

Data Out

to I/O Cell

(SOUT)

from I/O Cell

(REFCLK)

tHSIREFCLK

Reference Clock

Source

Synchronous Clock

to I/O Cell

(SSCLKOUT)

30

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