DF04M View Datasheet(PDF) - STMicroelectronics
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DF04M Datasheet PDF : 42 Pages
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AN1262 APPLICATION NOTE
Figure 13. PWM gain reduction by RC (secondary feedback II).
Not needed
in the L6590A
VFB
L6590
L6590D
L6590A
COMP
IF
RB
RB1
Vout
RH
CCOMP RC
VK
IC
TL431
CF RF
RL
A resistor RC in parallel to CCOMP, as shown in fig. 13, is useful to reduce the PWM gain ∆VCOMP/∆IC. In fact,
the resistor comes dynamically in parallel to RCOMP, thus reducing the equivalent value appearing at the numer-
ator of the gain. Moreover, since it diverts part of the current sourced by the pin COMP, the opto's transistor
carries less current and a slightly higher bias resistor RB can be used, thus giving some extra gain reduction.
An additional resistor, RB1, of some kΩ could be needed to guarantee sufficient bias to the TL431.
To be able to exploit the full dynamics of the error amplifier under worst case conditions, RC must not be lower
than 7 kΩ, which reduces the gain by a 1/0.35 ≅ 2.86 factor. RC values lower than 7 kΩ will reduce the gain
further on but will reduce also the maximum duty cycle allowed (worst case). Depending on the maximum duty
cycle specified for a given application, this can be acceptable.
Table 17 summarizes the situation for different values of RC.
Table 17. PWM gain reduction for different RC values
RC (kΩ)
RC // RCOMP (kΩ)
Dmax
PWM Gain
Reduction
7.5
4.09
0.7
2.2
7
3.94
0.7
2.29
6.8
3.87
0.68
2.32
6.2
3.67
0.62
2.45
5.6
3.45
0.55
2.61
5.1
3.26
0.49
2.76
4.7
3.09
0.44
2.91
4.3
2.91
0.38
3.09
3.9
2.72
0.32
3.31
3.6
2.57
0.28
3.5
KB
(RB multiplier)
1.24
1.25
1.25
1.27
1.28
1.29
1.31
1.32
1.33
1.34
Total Gain
Reduction
2.73
2.86
2.91
3.11
3.34
3.58
3.8
4.07
4.4
4.69
In this case the design procedure outlined in table 16 should be slightly modified as shown in table 18.
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