LC4256C-3FN256AI View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

LC4256C-3FN256AI

3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs

Lattice Semiconductor 

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C External Switching Characteristics

Over Recommended Operating Conditions

-25

-27

-3

-35

Parameter

Description1, 2, 3

Min. Max. Min. Max. Min. Max. Min. Max. Units

tPD

5-PT bypass combinatorial propagation

delay

—

2.5

—

2.7

—

3.0

—

3.5 ns

tPD_MC

20-PT combinatorial propagation delay

through macrocell

—

3.2

—

3.5

—

3.8

—

4.2 ns

tS

GLB register setup time before clock

1.8 — 1.8 — 2.0 — 2.0 — ns

tST

GLB register setup time before clock

with T-type register

2.0 — 2.0 — 2.2 — 2.2 — ns

tSIR

GLB register setup time before clock,

input register path

0.7 — 1.0 — 1.0 — 1.0 — ns

tSIRZ

GLB register setup time before clock

with zero hold

1.7 — 2.0 — 2.0 — 2.0 — ns

tH

GLB register hold time after clock

0.0 — 0.0 — 0.0 — 0.0 — ns

tHT

GLB register hold time after clock with

T-type register

0.0

—

0.0

—

0.0

—

0.0

—

ns

tHIR

GLB register hold time after clock, input

register path

0.9

—

1.0

—

1.0

—

1.0

—

ns

tHIRZ

GLB register hold time after clock, input

register path with zero hold

0.0

—

0.0

—

0.0

—

0.0

—

ns

tCO

GLB register clock-to-output delay

— 2.2 — 2.7 — 2.7 — 2.7 ns

tR

External reset pin to output delay

— 3.5 — 4.0 — 4.4 — 4.5 ns

tRW

External reset pulse duration

1.5 — 1.5 — 1.5 — 1.5

-

ns

tPTOE/DIS

Input to output local product term output

enable/disable

—

4.0

—

4.5

—

5.0

—

5.5 ns

tGPTOE/DIS

Input to output global product term

output enable/disable

— 5.0 — 6.5 — 8.0 — 8.0 ns

tGOE/DIS Global OE input to output enable/disable — 3.0 — 3.5 — 4.0 — 4.5 ns

tCW

Global clock width, high or low

1.1 — 1.3 — 1.3 — 1.3 — ns

tGW

Global gate width low (for low

transparent) or high (for high transparent)

1.1

—

1.3

—

1.3

—

1.3

—

ns

tWIR

Input register clock width, high or low

1.1 — 1.3 — 1.3 — 1.3

fMAX4

Clock frequency with internal feedback 400 — 333 — 322 — 322

fMAX (Ext.)

Clock frequency with external feedback,

[1/ (tS + tCO)]

250

—

222

—

212

—

212

1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.

2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

— ns

— MHz

— MHz

Timing v.3.2

22

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