LC4256C-3F256AI View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

LC4256C-3F256AI

3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs

Lattice Semiconductor 

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z External Switching Characteristics (Cont.)

Over Recommended Operating Conditions

-45

-5

-75

Parameter

Description1, 2, 3

Min. Max. Min. Max. Min. Max.

tPD

tPD_MC

5-PT bypass combinatorial propagation delay —

4.5

—

5.0

—

7.5

20-PT combinatorial propagation delay

through macrocell

—

5.8

—

6.0

—

8.0

tS

GLB register setup time before clock

2.9

—

3.0

—

4.5

—

tST

GLB register setup time before clock with T-

type register

3.1

—

3.2

—

4.7

—

tSIR

GLB register setup time before clock, input

register path

1.3

—

1.3

—

1.4

—

tSIRZ

GLB register setup time before clock with zero

hold

2.6

—

2.6

—

2.7

—

tH

GLB register hold time after clock

0.0

—

0.0

—

0.0

—

tHT

GLB register hold time after clock with T-type

register

0.0

—

0.0

—

0.0

—

tHIR

GLB register hold time after clock, input regis-

ter path

1.3

—

1.3

—

1.3

—

tHIRZ

GLB register hold time after clock, input regis-

ter path with zero hold

0.0

—

0.0

—

0.0

—

tCO

tR

tRW

tPTOE/DIS

GLB register clock-to-output delay

External reset pin to output delay

External reset pulse duration

Input to output local product term output

enable/disable

—

3.8

—

4.2

—

4.5

—

7.5

—

7.5

—

9.0

2.0

—

2.0

—

4.0

—

—

8.2

—

8.5

—

9.0

tGPTOE/DIS

Input to output global product term output

enable/disable

— 10.0 — 10.0 — 10.5

tGOE/DIS

tCW

tGW

Global OE input to output enable/disable

—

5.5

—

6.0

—

7.0

Global clock width, high or low

1.8

—

2.0

—

3.3

—

Global gate width low (for low transparent) or

high (for high transparent)

1.8

—

2.0

—

3.3

—

tWIR

Input register clock width, high or low

1.8

—

2.0

—

3.3

—

fMAX4

Clock frequency with internal feedback

200

—

200

—

168

—

tMAX (Ext.)

clock frequency with external feedback, [1 /

(tS + tCO)]

150

—

139

—

111

—

1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.

2. Measured using standard switching GRP loading of 1 and 1 output switching.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

Units

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

MHz

MHz

Timing v.2.2

25

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