Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000V/B/C Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
Parameter
Description
-2.5
-2.7
-3
-3.5
Units
tPDLi
Propagation Delay through
Transparent Latch to Output/
Feedback MUX
— 0.25 — 0.25 — 0.25 — 0.25 ns
tSRi
Asynchronous Reset or Set to
Output/Feedback MUX Delay
0.28 — 0.28 — 0.28 — 0.28 —
ns
tSRR
Asynchronous Reset or Set
Recovery Time
1.67 — 1.67 — 1.67 — 1.67 —
ns
Control Delays
tBCLK
tPTCLK
tBSR
tPTSR
tGPTOE
tPTOE
GLB PT Clock Delay
Macrocell PT Clock Delay
Block PT Set/Reset Delay
Macrocell PT Set/Reset Delay
Global PT OE Delay
Macrocell PT OE Delay
— 1.12 — 1.12 — 1.12 — 1.12 ns
— 0.87 — 0.87 — 0.87 — 0.87 ns
— 1.83 — 1.83 — 1.83 — 1.83 ns
— 1.11 — 1.41 — 1.51 — 1.61 ns
— 2.83 — 4.13 — 5.33 — 5.33 ns
— 1.83 — 2.13 — 2.33 — 2.83 ns
Timing v.3.2
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.
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