LC4256C-3F256AI View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LC4256C-3F256AI
Lattice Semiconductor
LC4256C-3F256AI Datasheet PDF : 99 Pages
| |||
Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000V/B/C Timing Adders1
Adder
Type
Base
Parameter
Description
-25
-27
-3
-35
Min. Max. Min. Max. Min. Max. Min. Max. Units
Optional Delay Adders
tINDIO
tEXP
tINREG
tMCELL
Input register delay
Product term expander
delay
— 0.95 — 1.00 — 1.00 — 1.00 ns
— 0.33 — 0.33 — 0.33 — 0.33 ns
tORP
tBLA
—
tROUTE
Output routing pool delay — 0.05 — 0.05 — 0.05 — 0.05 ns
Additional block loading
adder
— 0.03 — 0.05 — 0.05
—
0.05 ns
tIOI Input Adjusters
LVTTL_in
tIN, tGCLK_IN,
tGOE
Using LVTTL standard
LVCMOS33_in
tIN, tGCLK_IN, Using LVCMOS 3.3
tGOE
standard
LVCMOS25_in
tIN, tGCLK_IN, Using LVCMOS 2.5
tGOE
standard
LVCMOS18_in
tIN, tGCLK_IN, Using LVCMOS 1.8
tGOE
standard
PCI_in
tIN, tGCLK_IN, Using PCI compatible
tGOE
input
tIOO Output Adjusters
LVTTL_out
tBUF, tEN, tDIS
Output configured as
TTL buffer
— 0.60 — 0.60 — 0.60 — 0.60 ns
— 0.60 — 0.60 — 0.60 — 0.60 ns
— 0.60 — 0.60 — 0.60 — 0.60 ns
— 0.00 — 0.00 — 0.00 — 0.00 ns
— 0.60 — 0.60 — 0.60 — 0.60 ns
— 0.20 — 0.20 — 0.20 — 0.20 ns
LVCMOS33_out
tBUF, tEN, tDIS
Output configured as
3.3V buffer
— 0.20 — 0.20 — 0.20 — 0.20 ns
LVCMOS25_out
tBUF, tEN, tDIS
Output configured as
2.5V buffer
— 0.10 — 0.10 — 0.10 — 0.10 ns
LVCMOS18_out
tBUF, tEN, tDIS
Output configured as
1.8V buffer
— 0.00 — 0.00 — 0.00 — 0.00 ns
PCI_out
tBUF, tEN, tDIS
Output configured as
PCI compatible buffer
— 0.20 — 0.20 — 0.20 — 0.20 ns
Slow Slew
tBUF, tEN
Output configured for
slow slew rate
— 1.00 — 1.00 — 1.00 — 1.00 ns
Note: Open drain timing is the same as corresponding LVCMOS timing.
Timing v.3.2
1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.
35
Share Link: 