LC4256B-5T176I View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

Manufacturer

LC4256B-5T176I

3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs

Lattice Semiconductor 

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Timing Model

The task of determining the timing through the ispMACH 4000 family, like any CPLD, is relatively simple. The timing

model provided in Figure 11 shows the specific delay paths. Once the implementation of a given function is deter-

mined either conceptually or from the software report file, the delay path of the function can easily be determined

from the timing model. The Lattice design tools report the timing delays based on the same timing model for a par-

ticular design. Note that the internal timing parameters are given for reference only, and are not tested. The exter-

nal timing parameters are tested and guaranteed for every device. For more information on the timing model and

usage, please refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines.

Figure 11. ispMACH 4000 Timing Model

From

Feedback

IN

tIN

tIOI

SCLK

tGCLK_IN

tIOI

tINREG

tINDIO

tROUTE

tBLA

tMCELL

tEXP

tPTCLK

tBCLK

tPTSR

tBSR

OE

tGOE

tIOI

In/Out

Delays

Control

Delays

tGPTOE

tPTOE

Routing/GLB Delays

tPDb

tPDi

DATA

Q

tORP

C.E.

S/R

MC Reg.

Register/Latch

Delays

Feedback

tFBK

tBUF

tIOO

Out

tEN

tDIS

In/Out

Delays

Note: Italicized items are optional delay adders.

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