LC4064C-5T44I View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LC4064C-5T44I Datasheet PDF : 99 Pages
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Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000V/B/C Timing Adders1 (Cont.)
Adder
Type
Base
Parameter
Description
-5
-75
-10
Min. Max. Min. Max. Min. Max. Units
Optional Delay Adders
tINDIO
tINREG
Input register delay
tEXP
tMCELL
Product term expander delay
tORP
—
Output routing pool delay
tBLA
tROUTE
Additional block loading adder
tIOI Input Adjusters
LVTTL_in
tIN, tGCLK_IN,
tGOE
Using LVTTL standard
LVCMOS33_in
tIN, tGCLK_IN,
tGOE
Using LVCMOS 3.3 standard
LVCMOS25_in
tIN, tGCLK_IN,
tGOE
Using LVCMOS 2.5 standard
LVCMOS18_in
tIN, tGCLK_IN,
tGOE
Using LVCMOS 1.8 standard
PCI_in
tIN, tGCLK_IN,
tGOE
Using PCI compatible input
tIOO Output Adjusters
LVTTL_out
tBUF, tEN, tDIS Output configured as TTL buffer
LVCMOS33_out tBUF, tEN, tDIS Output configured as 3.3V buffer
LVCMOS25_out tBUF, tEN, tDIS Output configured as 2.5V buffer
LVCMOS18_out tBUF, tEN, tDIS Output configured as 1.8V buffer
PCI_out
tBUF, tEN, tDIS
Output configured as PCI compatible
buffer
— 1.00 — 1.00 — 1.00 ns
— 0.33 — 0.33 — 0.33 ns
— 0.05 — 0.05 — 0.05 ns
— 0.05 — 0.05 — 0.05 ns
— 0.60 — 0.60 — 0.60 ns
— 0.60 — 0.60 — 0.60 ns
— 0.60 — 0.60 — 0.60 ns
— 0.00 — 0.00 — 0.00 ns
— 0.60 — 0.60 — 0.60 ns
— 0.20 — 0.20 — 0.20 ns
— 0.20 — 0.20 — 0.20 ns
— 0.10 — 0.10 — 0.10 ns
— 0.00 — 0.00 — 0.00 ns
— 0.20 — 0.20 — 0.20 ns
Slow Slew
tBUF, tEN
Output configured for slow slew rate
— 1.00 — 1.00 — 1.00 ns
Note: Open drain timing is the same as corresponding LVCMOS timing.
Timing v.3.2
1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.
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