STM32F101C4T6ATR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM32F101C4T6ATR

Low-density access line, ARM-based 32-bit MCU with 16 or 32 KB Flash, 5 timers, ADC and 4 communication interfaces

STMicroelectronics 

STM32F101x4, STM32F101x6

Electrical characteristics

5.3.14

Figure 26. I/O AC characteristics definition

90%

50%

10%

10%

50%

90%

EXT ERNAL

O UTP UT

ON 50pF

tr(I O)out

tr(I O)out

T

Maximum fr equency is achieved if (tr + tf) ≤ 2/3) T and if the duty cycle is (45-55%)

when loaded by 50pF

ai14131

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up

resistor, RPU (see Table 34).

Unless otherwise specified, the parameters given in Table 37 are derived from tests

performed under the ambient temperature and VDD supply voltage conditions summarized

in Table 8.

Table 37. NRST pin characteristics

Symbol

Parameter

Conditions Min Typ

Max Unit

VIL(NRST)(1) NRST Input low level voltage

VIH(NRST)(1) NRST Input high level voltage

–0.5

2

0.8

V

VDD+0.5

Vhys(NRST)

NRST Schmitt trigger voltage

hysteresis

200

mV

RPU

Weak pull-up equivalent resistor(2) VIN = VSS

30

40

VF(NRST)(1) NRST Input filtered pulse

VNF(NRST)(1) NRST Input not filtered pulse

300

50

kΩ

100

ns

ns

1. Guaranteed by design, not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

. the series resistance must be minimum (~10% order)

Figure 27. Recommended NRST pin protection

External

reset circuit(1)

VDD

NRST(2)

RPU

0.1 µF

Internal reset

Filter

STM32F10x

ai14132d

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 37. Otherwise the reset will not be taken into account by the device.

Doc ID 15058 Rev 5

57/79

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