STM32F101C4T6ATR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM32F101C4T6ATR

Low-density access line, ARM-based 32-bit MCU with 16 or 32 KB Flash, 5 timers, ADC and 4 communication interfaces

STMicroelectronics 

Electrical characteristics

STM32F101x4, STM32F101x6

5.3.17

Note:

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 42 are derived from tests

performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage

conditions summarized in Table 8.

It is recommended to perform a calibration after each power-up.

Table 42. ADC characteristics

Symbol

Parameter

Conditions

Min

Typ Max Unit

VDDA

fADC

fS(1)

Power supply

ADC clock frequency

Sampling rate

fTRIG(1) External trigger frequency

VAIN Conversion voltage range(2)

RAIN(1) External input impedance

RADC(1) Sampling switch resistance

CADC(1)

Internal sample and hold

capacitor

tCAL(1) Calibration time

tlat(1)

Injection trigger conversion

latency

tlatr(1)

Regular trigger conversion

latency

tS(1) Sampling time

tSTAB(1) Power-up time

tCONV(1)

Total conversion time

(including sampling time)

fADC = 14 MHz

See Equation 1 and

Table 43 for details

fADC = 14 MHz

fADC = MHz

fADC = 14 MHz

fADC = 14 MHz

fADC = 14 MHz

2.4

0.6

0.05

0 (VSSA or VREF-

tied to ground)

3.6

14

1

823

17

VREF+

V

MHz

MHz

kHz

1/fADC

V

50

kΩ

1

kΩ

8

pF

5.9

83

0.214

3(3)

0.143

2(3)

0.107

17.1

1.5

239.5

0

0

1

1

18

14 to 252 (tS for sampling +12.5 for

successive approximation)

µs

1/fADC

µs

1/fADC

µs

1/fADC

µs

1/fADC

µs

µs

1/fADC

1. Guaranteed by design, not tested in production.

2. VREF+ is internally connected to VDDA and VREF- is be internally connected to VSSA.

3. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 42.

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Doc ID 15058 Rev 5

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