ST92250V2TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92250V2TC

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

ST92F124/F150/F250 - INTERRUPTS

INTERRUPT REGISTERS (Cont’d)

INTERRUPT PRIORITY LEVEL REGISTER LOW

(SIPLRL)

R253 - Read/Write

Register Page: Page 60

Reset Value : 1111 1111

7

0

PL2H PL1H PL2G PL1G PL2F PL1F PL2E PL1E

Bits 7:6 = PL2H, PL1H: INTH0,H1 Priority Level.

Bits 5:4 = PL2G, PL1G: INTG0, G1 Priority Level.

Bits 3:2 = PL2F, PL1F: INTF0, F1 Priority Level.

Bits 1:0 = PL2E, PL1E: INTE0, E1 Priority Level.

These bits are set and cleared by software.

The priority is a three-bit value. The LSB is fixed by

hardware at 0 for even channels and at 1 for odd

channels

Table 22. PL Bit Assignment

Interrupt Channel

Pair

INTH0

INTH1

INTG0

INTG1

INTF0

INTF1

INTE0

INTE1

3-bit Priority Level

PL2H

PL1H

0

PL2H

PL1H

1

PL2G

PL1G

0

PL2G

PL1G

1

PL2F

PL1F

0

PL2F

PL1F

1

PL2E

PL1E

0

PL2E

PL1E

1

Table 23. PL bit Meaning

PL2x

0

0

1

1

PL1x

0

1

0

1

Hardware bit

0

1

0

1

0

1

0

1

Priority

0 (Highest)

1

2

3

4

5

6

7 (Lowest)

Interrupt Channel

Pair

INTE0

INTE1

INTF0

INTF1

INTG0

INTG1

INTH0

INTH1

Priority Level

PL2E PL1E

0

PL2E PL1E

1

PL2F PL1F

0

PL2F PL1F

1

PL2G PL1G

0

PL2G PL1G

1

PL2H PL1H

0

PL2H PL1H

1

INTERRUPT FLAG REGISTER HIGH

(SFLAGRH)

R254 - Read Only

Register Page: 60

Reset Value : 0000 0000

7

0

-

-

-

-

-

-

-

OUFI0

Bit 0 = OUFI0 : Overrun flag for INTI0

This bit is set and cleared by hardware. It indicates

if more than one interrupt event occured on INTI0

before the IPI0 bit in the SIPRH register has been

cleared.

0 : No overrun

1 : Overrun has occurred on INTI0

INTERRUPT FLAG REGISTER LOW

(SFLAGRL)

R255 - Read Only

Register Page: 60

Reset Value : 0000 0000

7

0

OUFH1 OUFH0 OUFG1 OUFG0 OUFF1 OUFF0 OUFE1 OUFE0

Bits 7:0 = OUFxx : Overrun flag for channel xx

These bits are set and cleared by hardware. They

indicate if more than one interrupt event occurs on

the associated channel before the pending bit in

the SIPRL register has been cleared.

0 : No overrun

1 : Overrun has occurred on channel xx

111/429

9

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