ST92F250V9TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F250V9TC

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

ST92F124/F150/F250 - INTERRUPTS

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)

5.12.4 Programming Considerations

The following paragraphs give some guidelines for

designing an application program.

5.12.4.1 Procedure for Entering/Exiting STOP

mode

9. Poll the wake-up pending bits to determine

which wake-up line caused the exit from STOP

mode.

10.Clear the wake-up pending bit that was set.

5.12.4.2 Simultaneous Setting of Pending Bits

1. Program the polarity of the trigger event of

external wake-up lines by writing registers

WUTRH and WUTRL.

2. Check that at least one mask bit (registers

WUMRH, WUMRL) is equal to 1 (so at least

one external wake-up line is not masked).

3. Reset at least the unmasked pending bits: this

allows a rising edge to be generated on the

INTD1 channel when the trigger event occurs

(an interrupt on channel INTD1 is recognized

when a rising edge occurs).

4. Set the ID1S bit in the WUCTRL register and

set the WKUP-INT bit.

5. To generate an interrupt on channel INTD1, bits

EITR.1 (R242.7, Page 0) and EIMR.1 (R244.7,

Page 0) must be set and bit EIPR.7 must be

reset. Bits 7 and 6 of register R245, Page 0

must be written with the desired priority level for

interrupt channel INTD1.

It is possible that several simultaneous events set

different pending bits. In order to accept subse-

quent events on external wake-up/interrupt lines, it

is necessary to clear at least one pending bit: this

operation allows a rising edge to be generated on

the INTD1 line (if there is at least one more pend-

ing bit set and not masked) and so to set EIPR.7

bit again. A further interrupt on channel INTD1 will

be serviced depending on the status of bit EIMR.7.

Two possible situations may arise:

1. The user chooses to reset all pending bits: no

further interrupt requests will be generated on

channel INTD1. In this case the user has to:

– Reset EIMR.7 bit (to avoid generating a spuri-

ous interrupt request during the next reset op-

eration on the WUPRH register)

– Reset WUPRH register using a read-modify-

write instruction (AND, BRES, BAND)

– Clear the EIPR.7 bit

6. Reset the STOP bit in register WUCTRL and

the EX_STP bit in the CLK_FLAG register

(R242.7, Page 55). Refer to the RCCU chapter.

7. To enter STOP mode, write the sequence 1, 0,

1 to the STOP bit in the WUCTRL register with

three consecutive write operations.

8. The code to be executed just after the STOP

sequence must check the status of the STOP

and RCCU EX_STP bits to determine if the ST9

entered STOP mode or not (See “Wake-up

Mode Selection” on page 114. for details). If the

ST9 did not enter in STOP mode it is necessary

to reloop the procedure from the beginning, oth-

erwise the procedure continues from next point.

– Reset the WUPRL register using a read-mod-

ify-write instruction (AND, BRES, BAND)

2. The user chooses to keep at least one pending

bit active: at least one additional interrupt

request will be generated on the INTD1 chan-

nel. In this case the user has to reset the

desired pending bits with a read-modify-write

instruction (AND, BRES, BAND). This operation

will generate a rising edge on the INTD1 chan-

nel and the EIPR.7 bit will be set again. An

interrupt on the INTD1 channel will be serviced

depending on the status of EIMR.7 bit.

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