ST92F124JCV2TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F124JCV2TC

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA)

6.6 DMA REGISTERS

As each peripheral DMA channel has its own spe-

cific control registers, the following register list

should be considered as a general example. The

names and register bit allocations shown here

may be different from those found in the peripheral

chapters.

DMA COUNTER POINTER REGISTER (DCPR)

Read/Write

Address set by Peripheral

Reset value: undefined

7

0

C7 C6 C5 C4 C3 C2 C1 RM

Bit 7:1 = C[7:1]: DMA Transaction Counter Point-

er.

Software should write the pointer to the DMA

Transaction Counter in these bits.

Bit 0 = RM: Register File/Memory Selector.

This bit is set and cleared by software.

0: DMA transactions are with memory (see also

DAPR.DP)

1: DMA transactions are with the Register File

GENERIC EXTERNAL PERIPHERAL INTER-

RUPT AND DMA CONTROL (IDCR)

Read/Write

Address set by Peripheral

Reset value: undefined

7

0

IP DM IM PRL2 PRL1 PRL0

Bit 5 = IP: Interrupt Pending.

This bit is set by hardware when the Trigger Event

occurs. It is cleared by hardware when the request

is acknowledged. It can be set/cleared by software

in order to generate/cancel a pending request.

0: No interrupt pending

1: Interrupt pending

Bit 3 = IM: End of block Interrupt Mask.

This bit is set and cleared by software.

0: No End of block interrupt request is generated

when IP is set

1: End of Block interrupt is generated when IP is

set. DMA requests depend on the DM bit value

as shown in the table below.

DM IM Meaning

1

0

A DMA request generated without End of Block

interrupt when IP=1

1

1

A DMA request generated with End of Block in-

terrupt when IP=1

0

0

No End of block interrupt or DMA request is

generated when IP=1

0

1

An End of block Interrupt is generated without

associated DMA request (not used)

Bit 2:0 = PRL[2:0]: Source Priority Level.

These bits are set and cleared by software. Refer

to Section 6.2 DMA PRIORITY LEVELS for a de-

scription of priority levels.

PRL2 PRL1 PRL0 Source Priority Level

0

0

0

0 Highest

0

0

1

1

0

1

0

2

0

1

1

3

1

0

0

4

1

0

1

5

1

1

0

6

1

1

1

7 Lowest

DMA ADDRESS POINTER REGISTER (DAPR)

Read/Write

Address set by Peripheral

Reset value: undefined

7

0

A7 A6 A5 A4 A3 A2 A1 PS

Bit 7:1 = A[7:1]: DMA Address Register(s) Pointer

Software should write the pointer to the DMA Ad-

dress Register(s) in these bits.

Bit 4 = DM: DMA Request Mask.

This bit is set and cleared by software. It is also

cleared when the transaction counter reaches

zero (unless SWAP mode is active).

0: No DMA request is generated when IP is set.

1: DMA request is generated when IP is set

Bit 0 = PS: Memory Segment Pointer Selector:

This bit is set and cleared by software. It is only

meaningful if DCPR.RM=0.

0: The ISR register is used to extend the address

of data transferred by DMA (see MMU chapter).

1: The DMASR register is used to extend the ad-

dress of data transferred by DMA (see MMU

chapter).

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