ST92F124CR9QB View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F124CR9QB

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

ST92F124/F150/F250 - RESET AND CLOCK CONTROL UNIT (RCCU)

CLOCK MANAGEMENT (Cont’d)

7.3.6 Interrupt Generation

System clock selection modifies the CLKCTL and

CLK_FLAG registers.

The clock control unit generates an external inter-

rupt request (INTD0) in the following conditions:

– when CK_AF and CLOCK2/16 are selected or

deselected as system clock source,

– when the system clock restarts after a hardware

stop (when the STOP MODE feature is availa-

ble on the specific device).

– when the PLL loses the programmed frequency

in which it was locked, and when it re-locks

This interrupt can be masked by resetting the

INT_SEL bit in the CLKCTL register. Note that this

is the only case in the ST9 where an interrupt is

generated with a high to low transition.

Table 27. Summary of Operating Modes using main Crystal Controlled Oscillator

MODE

PLL x BY 14

PLL x BY 10

PLL x BY 8

PLL x BY 6

SLOW 1

SLOW 2

SLOW3

WFI

LOW POW-

ER WFI 1

LOW POW-

ER WFI 2

RESET

INTCLK

CPUCLK DIV2 PRS0-2

CSU_CKSEL

MX0-1

DX2-0

LPOWFI

WFI_CK

SEL

XT_DIV16

XTAL/2

x (14/D)

INTCLK/

N

1

N-1

1

1 0 D-1

X

X

1

XTAL/2

x (10/D)

INTCLK/

N

1

N-1

1

0 0 D-1

X

X

1

XTAL/2

x (8/D)

INTCLK/

N

1

N-1

1

1 1 D-1

X

X

1

XTAL/2

x (6/D)

INTCLK/

N

1

N-1

1

0 1 D-1

X

X

1

XTAL/2

INTCLK/

N

1

N-1

X

X 111

X

X

1

XTAL/32

INTCLK/

N

1

N-1

X

X

X

X

X

0

CK_AF CK_AF/N X N-1

X

X

X

X

X

X

If LPOWFI=0, no changes occur on INTCLK, but CPUCLK is stopped anyway.

XTAL/32 STOP 1

X

X

X

X

1

0

X

CK_AF STOP 1

X

XTAL/2 INTCLK 1

0

X

X

X

1

1

X

0

00 111

0

0

1

EXAMPLE

XTAL=4.4

MHz

2.2*10/2

= 11MHz

11MHz

1

0

1

00 001

X

1

131/429

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