ST92F124JDV2TC View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST92F124JDV2TC
STMicroelectronics
ST92F124JDV2TC Datasheet PDF : 429 Pages
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ST92F124/F150/F250 - EXTERNAL MEMORY INTERFACE (EXTMI)
EXTERNAL MEMORY SIGNALS (Cont’d)
8.2.5 PORT 0
If Port 0 is used as a bit programmable parallel I/O
port, it has the same features as a regular port.
When set as an Alternate Function, it is used as
the External Memory interface: it outputs the mul-
tiplexed Address (8 LSB: A[7:0]) / Data bus D[7:0].
8.2.6 PORT 1
If Port 1 is used as a bit programmable parallel I/O
port, it has the same features as a regular port.
When set as an Alternate Function, it is used as
the external memory interface to provide the ad-
dress bits A[15:8].
Figure 74. Application Example (MC=0)
8.2.7 PORT 9 [7:2]
If Port 9 is available and used as a bit programma-
ble I/O port, it has the same features as a regular
port. If the MMU is available on the device and
Port 9 is set as an Alternate Function, Port 9[7:2] is
used as the external memory interface to provide
the 6 MSB of the address (A[21:16]).
Note: For the ST92F250 device, since A[18:17]
share the same pins as SDA1 and SCL1 of I²C_1,
these address bits are not available when the
I²C_1 is in use (when I2CCR.PE bit is set).
RW
DS
P0
D[7:0]
ST9
A[7:0]
D[7:0]
Q[7:0]
AS
LE
OE
W
G
Q[7:0]
RAM
2 Mbytes
A[20:0]
E
P9[6:2], P1 A[20:8]
P9.7 A21
Figure 75. Application Example (MC=1)
LATCH
DS
Q[7:0]
A[20:0]
E
ROM
2 Mbytes
WEN
OEN
P0
D[7:0]
ST9
A[7:0]
D[7:0]
Q[7:0]
ALE
LE
OE
W
G
Q[7:0]
RAM
2 Mbytes
A[20:0]
E
P9[6:2], P1 A[20:8]
P9.7 A21
LATCH
DS
Q[7:0]
A[20:0]
E
ROM
2 Mbytes
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