ST92250JCR2QC View Datasheet(PDF) - STMicroelectronics
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Description
Manufacturer
ST92250JCR2QC
STMicroelectronics
ST92250JCR2QC Datasheet PDF : 429 Pages
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TIMER/WATCHDOG (WDT)
TIMER/WATCHDOG (Cont’d)
10.1.4 WDT Interrupts
The Timer/Watchdog issues an interrupt request
at every End of Count, when this feature is ena-
bled.
A pair of control bits, IA0S (EIVR.1, Interrupt A0 se-
lection bit) and TLIS (EIVR.2, Top Level Input Se-
lection bit) allow the selection of 2 interrupt sources
(Timer/Watchdog End of Count, or External Pin)
handled in two different ways, as a Top Level Non
Maskable Interrupt (Software Reset), or as a
source for channel A0 of the external interrupt logic.
A block diagram of the interrupt logic is given in
Figure 89.
Note: Software traps can be generated by setting
the appropriate interrupt pending bit.
Table 34 below, shows all the possible configura-
tions of interrupt/reset sources which relate to the
Timer/Watchdog.
A reset caused by the watchdog will set bit 6,
WDGRES of R242 - Page 55 (Clock Flag Regis-
ter). See section CLOCK CONTROL REGIS-
TERS.
Figure 89. Interrupt Sources
TIMER WATCHDOG
INT0
NMI
RESET
WDGEN (WCR.6)
0
MUX
1
INTA0 REQUEST
IA0S (EIVR.1)
0
MUX
1
TOP LEVEL
INTERRUPT REQUEST
TLIS (EIVR.2)
VA00293
Table 34. Interrupt Configuration
Control Bits
WDGEN
IA0S
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
TLIS
0
1
0
1
0
1
0
1
Enabled Sources
Reset
INTA0
WDG/Ext Reset
WDG/Ext Reset
WDG/Ext Reset
WDG/Ext Reset
SW TRAP
SW TRAP
Ext Pin
Ext Pin
Ext Reset
Ext Reset
Ext Reset
Ext Reset
Timer
Timer
Ext Pin
Ext Pin
Top Level
SW TRAP
Ext Pin
SW TRAP
Ext Pin
Timer
Ext Pin
Timer
Ext Pin
Operating Mode
Watchdog
Watchdog
Watchdog
Watchdog
Timer
Timer
Timer
Timer
Legend:
WDG = Watchdog function
SW TRAP = Software Trap
Note: If IA0S and TLIS = 0 (enabling the Watchdog EOC as interrupt source for both Top Level and INTA0
interrupts), only the INTA0 interrupt is taken into account.
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