ST92250JDV2TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92250JDV2TC

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

MULTIFUNCTION TIMER (MFT)

MULTIFUNCTION TIMER (Cont’d)

10.4.3.13 Autodiscrimination Mode

The phase between two pulses (respectively on in-

put pin B and input pin A) generates a one step up

(or down) count, so that the up/down control and

the counter clock are both external. Thus, if the ris-

ing edge of TxINB arrives when TxINA is at a low

level, the timer is incremented (no action if the ris-

ing edge of TxINB arrives when TxINA is at a high

level). If the falling edge of TxINB arrives when

TxINA is at a low level, the timer is decremented

(no action if the falling edge of TxINB arrives when

TxINA is at a high level).

Setting the UDC bit in the TCR register has no ef-

fect in this configuration.

ture), while the signal applied to input pin B is used

as the clock for the prescaler.

(*) The timer is in One shot mode and REG0R in

reload mode

10.4.3.14 TxINA = Trigger - TxINB = Ext. Clock

The signal applied to input pin A acts as a trigger

signal on REG0R, initiating the action for which the

register was programmed (i.e. a reload or cap-

10.4.3.15 TxINA = Ext. Clock - TxINB = Trigger

The signal applied to input pin B acts as a trigger,

performing a capture on REG1R, while the signal

applied to input pin A is used as the clock for the

prescaler.

10.4.3.16 TxINA = Trigger - TxINB = Gate

The signal applied to input pin A acts as a trigger

signal on REG0R, initiating the action for which the

register was programmed (i.e. a reload or cap-

ture), while the signal applied to input pin B acts as

a gate signal for the internal clock (i.e. the counter

runs only when the gate signal is at a low level).

196/429

9

Share Link: