ST92150CR1TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92150CR1TC

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

SERIAL PERIPHERAL INTERFACE (SPI)

10.7 SERIAL PERIPHERAL INTERFACE (SPI)

10.7.1 Introduction

The Serial Peripheral Interface (SPI) allows full-

duplex, synchronous, serial communication with

external devices. An SPI system may consist of a

master and one or more slaves or a system in

which devices may be either masters or slaves.

The SPI is normally used for communication be-

tween the microcontroller and external peripherals

or another Microcontroller.

Refer to the Pin Description chapter for the device-

specific pin-out.

10.7.2 Main Features

■ Full duplex, three-wire synchronous transfers

■ Master or slave operation

■ Maximum slave mode frequency = INTCLK/2.

■ Programmable prescalers for a wide range of

baud rates

■ Programmable clock polarity and phase

■ End of transfer interrupt flag

■ Write collision flag protection

■ Master mode fault protection capability.

10.7.3 General Description

The SPI is connected to external devices through

4 alternate function pins:

– MISO: Master In Slave Out pin

– MOSI: Master Out Slave In pin

– SCK: Serial Clock pin

– SS: Slave select pin

To use any of these alternate functions (input or

output), the corresponding I/O port must be pro-

grammed as alternate function output.

A basic example of interconnections between a

single master and a single slave is illustrated on

Figure 120.

The MOSI pins are connected together as are

MISO pins. In this way data is transferred serially

between master and slave.

When the master device transmits data to a slave

device via MOSI pin, the slave device responds by

sending data to the master device via the MISO

pin. This implies full duplex transmission with both

data out and data in synchronized with the same

clock signal (which is provided by the master de-

vice via the SCK pin).

Thus, the byte transmitted is replaced by the byte

received and eliminates the need for separate

transmit-empty and receiver-full bits. A status flag

is used to indicate that the I/O operation is com-

plete.

Various data/clock timing relationships may be

chosen (see Figure 123) but master and slave

must be programmed with the same timing mode.

Figure 120. Serial Peripheral Interface Master/Slave

MASTER

MSBit

LSBit

8-BIT SHIFT REGISTER

MISO

MOSI

MISO

MOSI

MSBit

SLAVE

LSBit

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

SCK

SS +5V

SCK

SS

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