SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 123. Data Clock Timing Diagram
SCK
(CPOL = 1)
CPHA =1
SCK
(CPOL = 0)
MISO
(from master)
MSBit Bit 6
MOSI
(from slave)
MSBit Bit 6
SS
(to slave)
CAPTURE STROBE
Bit 5 Bit 4
Bit 5 Bit 4
Bit3 Bit 2
Bit3 Bit 2
Bit 1 LSBit
Bit 1 LSBit
SCK
(CPOL = 1)
SCK
(CPOL = 0)
CPHA =0
MISO
(from master)
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
MOSI
(from slave)
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
SS
(to slave)
CAPTURE STROBE
Note: This figure should not be used as a replacement for parametric information.
Refer to the SPI Timing table in the Electrical Characteristics Section.
255/429
9