ST92F150CR2TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F150CR2TC

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E³ ™ (EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

STMicroelectronics 

J1850 Byte Level Protocol Decoder (JBLPD)

J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)

10.9.7 Register Description

The JBLPD peripheral uses 48 registers that are

mapped in a single page of the ST9 register file.

Twelve registers are mapped from R240 (F0h) to

R251 (FBh): these registers are usually used to

control the JBLPD. See Section 10.9.7.1 Un-

Stacked Registers for a detailed description of

these registers.

Thirty-six registers are mapped from R252 (FCh)

to R255 (FFh). This is obtained by creating 9 sub-

pages, each containing 4 registers, mapped in the

same register addresses; 4 bits (RSEL[3:0]) of a

register (OPTIONS) are used to select the current

sub-page. See Section 10.9.7.2 Stacked Regis-

ters section for a detailed description of these reg-

isters.

The ST9 Register File page used is 23 (17h).

NOTE: Bits marked as “Reserved” should be left at

their reset value to guarantee software compatibil-

ity with future versions of the JBLPD.

Figure 141. JBLPD Register Map

R240 (F0h)

R241 (F1h)

R242 (F2h)

R243 (F3h)

R244 (F4h)

R245 (F5h)

R246 (F6h)

R247 (F7h)

R248 (F8h)

R249 (F9h)

R250 (FAh)

R251 (FBh)

STATUS

TXDATA

RXDATA

TXOP

CLKSEL

CONTROL

PADDR

ERROR

IVR

PRLR

IMR

OPTIONS

R252 (FCh)

R253 (FDh)

R254 (FEh)

R255 (FFh)

CREG0

CREG1

CREG2

CREG3

RDAPR

RDCPR

TDAPR

TDCPR

FREG28

FREG24FREG29

FREG20FREG25FREG30

FREG16FREG21FREG26FREG31

FREG12FREG17FREG22FREG27

FREG8 FREG13FREG18FREG23

FREG4 FREG9 FREG14FREG19

FREG0 FREG5 FREG10FREG15

FREG1 FREG6 FREG11

FREG2 FREG7

FREG3

304/429

9

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