ST92F124/F150/F250 - REGISTER AND MEMORY MAP
Table 17. Detailed Register Map
Page
(Dec)
N/A
0
2
Block
Core
I/O
Port
0:5
INT
WDT
I/O
Port
0
I/O
Port
1
I/O
Port
2
I/O
Port
3
Reg.
No.
R230
R231
R232
R233
R234
R235
R236
R237
R238
R239
R224
R225
R226
R227
R228
R229
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R240
R241
R242
R244
R245
R246
R248
R249
R250
R252
R253
R254
Register
Name
CICR
FLAGR
RP0
RP1
PPR
MODER
USPHR
USPLR
SSPHR
SSPLR
P0DR
P1DR
P2DR
P3DR
P4DR
P5DR
EITR
EIPR
EIMR
EIPLR
EIVR
NICR
WDTHR
WDTLR
WDTPR
WDTCR
WCR
P0C0
P0C1
P0C2
P1C0
P1C1
P1C2
P2C0
P2C1
P2C2
P3C0
P3C1
P3C2
Description
Central Interrupt Control Register
Flag Register
Pointer 0 Register
Pointer 1 Register
Page Pointer Register
Mode Register
User Stack Pointer High Register
User Stack Pointer Low Register
System Stack Pointer High Reg.
System Stack Pointer Low Reg.
Port 0 Data Register
Port 1 Data Register
Port 2 Data Register
Port 3 Data Register
Port 4 Data Register
Port 5 Data Register
External Interrupt Trigger Register
External Interrupt Pending Reg.
External Interrupt Mask-bit Reg.
External Interrupt Priority Level Reg.
External Interrupt Vector Register
Nested Interrupt Control
Watchdog Timer High Register
Watchdog Timer Low Register
Watchdog Timer Prescaler Reg.
Watchdog Timer Control Register
Wait Control Register
Port 0 Configuration Register 0
Port 0 Configuration Register 1
Port 0 Configuration Register 2
Port 1 Configuration Register 0
Port 1 Configuration Register 1
Port 1 Configuration Register 2
Port 2 Configuration Register 0
Port 2 Configuration Register 1
Port 2 Configuration Register 2
Port 3 Configuration Register 0
Port 3 Configuration Register 1
Port 3 Configuration Register 2
Reset
Value
Hex.
87
00
xx
xx
xx
E0
xx
xx
xx
xx
FF
FF
FF
1111 111x
FF
FF
00
00
00
FF
x6
00
FF
FF
FF
12
7F
00
00
00
00
00
00
FF
00
00
1111 111x
0000 000x
0000 000x
Doc.
Page
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41
151
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163
108
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151
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