LPC2364 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

LPC2364

Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC

NXP Semiconductors. 

NXP Semiconductors

LPC2364/65/66/67/68

Single-chip 16-bit/32-bit microcontrollers

7.18.1 Features

• I2C0 is a standard I2C compliant bus interface with open-drain pins.

• I2C1 and I2C2 use standard I/O pins and do not support powering off of individual

devices connected to the same bus lines.

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I2C-bus can be used for test and diagnostic purposes.

7.19 I2S-bus serial I/O controllers

The I2S-bus provides a standard communication interface for digital audio applications.

The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line,

and one word select signal. The basic I2S connection has one master, which is always the

master, and one slave. The I2S interface on the LPC2364/65/66/67/68 provides a

separate transmit and receive channel, each of which can operate as either a master or a

slave.

7.19.1 Features

• The interface has separate input/output channels each of which can operate in master

or slave mode.

• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

• Mono and stereo audio data supported.

• The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1,

48) kHz.

• Configurable word select period in master mode (separately for I2S input and output).

• Two 8-word FIFO data buffers are provided, one for transmit and one for receive.

• Generates interrupt requests when buffer levels cross a programmable boundary.

• Two DMA requests, controlled by programmable buffer levels. These are connected

to the GPDMA block.

• Controls include reset, stop and mute options separately for I2S input and I2S output.

LPC2364_65_66_67_68

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7.1 — 16 October 2013

© NXP B.V. 2013. All rights reserved.

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