LT3071MPUFD View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LT3071MPUFD

5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator with Analog Margining

Linear Technology 

LT3071

PIN FUNCTIONS

IMON (Pin 21): Output Current Monitor. The IMON pin

sources a current typically equal to IOUT/2500 or 400µA

per amp of output current. Terminating this pin with a

resistor to GND produces a voltage proportional to IOUT .

For example, at IOUT = 5A, IMON typically sources 2mA.

With a 1k resistor to GND, this produces 2V. If IMON is

unused, tie this pin to VBIAS.

MARGA (Pin 22): Analog Margining. This pin margins the

output voltage over a continuous analog range of ±10%.

Tying this pin to GND adjusts output voltage by –10%.

Driving this pin to 1.2V adjusts output voltage by +10%. A

voltage source or a voltage output DAC is ideal for driving

this pin. If the MARGA function is not used, either float

this pin or terminate with a 1nF capacitor to GND.

VO0, VO1 and VO2 (Pins 23, 24, 25): Output Voltage Se-

lect. These three-state pins combine to select a nominal

output voltage from 0.8V to 1.8V in increments of 50mV.

Output voltage is limited to 1.8V maximum by an internal

override of VO1 when VO2 = high. The input logic low

threshold is less than 250mV referenced to GND and the

logic high threshold is greater than VBIAS – 250mV. The

range between these two thresholds as set by a window

comparator defines the logic Hi-Z state. See Table 1 in the

Applications Information section that defines the VO2, VO1

and VO0 settings versus VOUT .

BIAS (Pin 27): Bias Supply. This pin supplies current to

the internal control circuitry and the output stage driving

the pass transistor. The LT3071 requires a minimum 2.2µF

bypass capacitor for stability and proper operation. To

ensure proper operation, the BIAS voltage must satisfy

the following conditions: 2.2V ≤ VBIAS ≤ 3.6V and VBIAS ≥

(1.25 • VOUT + 1V). For VOUT ≤ 0.95V, the minimum BIAS

voltage is limited to 2.2V.

EN (Pin 28): Enable. This pin enables/disables the output

device only. The internal reference and all support functions

are active if VBIAS is above its UVLO threshold. Pulling EN

low keeps the reference circuit active, but disables the

output pass transistor and puts the LT3071 into a low

power nap mode. The maximum rising EN threshold is

ratioed to 0.56% of VBIAS and the minimum falling ENx

threshold is 0.36% of VBIAS. Drive the EN pin with either

a digital logic port or an open-collector NPN or an open-

drain NMOS terminated with a pull-up resistor to VBIAS.

The pull-up resistor must be less than 35k to meet the VIH

condition of the EN pin. If unused, connect EN to BIAS.

+

VBIAS

+

VIN

BIAS

EN

PWRGD

IN

SENSE

VO0 LT3071 OUT

VO1

RP

VO2

MARGA

IMON

VIOC

REF/BYP

GND

LOAD

RP

3071 F01

Figure 1. Kelvin Sense Connection

For more information www.linear.com/LT3071

3071fc

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