LTC1066-1CS View Datasheet(PDF) - Linear Technology
Part Name
Description
Manufacturer
LTC1066-1CS
Linear Technology
LTC1066-1CS Datasheet PDF : 16 Pages
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LTC1066-1
APPLICATIONS INFORMATION
Transient Response and Settling Time
The LTC1066-1 exhibits two different transient behaviors.
First, during power-up the DC correcting loop will settle
after the voltage offset of the internal switched-capacitor
network is stored across the feedback capacitor CF (see
Block Diagram). It takes approximately five time constants
(5RFCF) for settling to 1%. Second, following DC loop
settling, the filter reaches steady state. The filter transient
response is then defined by the frequency characteristics
of the internal switched-capacitor lowpass filter. Figure 5
shows details.
DC loop settling is also observed if, at steady state, the DC
offset of the internal switched-capacitor network suddenly
changes. A sudden change may occur if the clock fre-
quency is instantaneously stepped to a value above 1MHz.
ts
INPUT
90%
OUTPUT
50%
td
and on the value of the power supplies. With proper layout
techniques the values of the clock feedthrough are shown
on Table 7.
Table 7. Clock Feedthrough
POWER SUPPLY
50:1
Single 5V
±5V
±7.5V
70µVRMS
100µVRMS
160µVRMS
100:1
90µVRMS
200µVRMS
650µVRMS
Wideband Noise
The wideband noise of the filter is the total RMS value of
the device’s noise spectral density and is used to deter-
mine the operating signal-to-noise ratio. Most of its fre-
quency contents lie within the filter passband and cannot
be reduced with post filtering. For instance, the LTC1066-
1 wideband noise at ±5V supply is 100µVRMS, 95µVRMS of
which have frequency contents from DC up to the filter’s
cutoff frequency. The total wideband noise (µVRMS) is
nearly independent of the value of the clock. The clock
feedthrough specifications are not part of the wideband
noise. Table 8 lists the typical wideband noise for each
supply.
10%
tr
RISE TIME (tr)
SETTLING TIME (ts)
DELAY TIME (td)
50:1 ELLIPTIC
0.43
fCUTOFF
±5%
3.4 ±5%
fCUTOFF
0.709
fCUTOFF
±5%
100:1 LINEAR PHASE
0.43
fCUTOFF
±5%
2.05
fCUTOFF
±5%
0.556 ±5%
fCUTOFF
1066-1 F05
Figure 5. Transient Response
Table 8. Wideband Noise
POWER SUPPLY
50:1
Single 5V
±5V
±7.5V
90µVRMS
100µVRMS
106µVRMS
100:1 (Pin 8 to GND)
80µVRMS
85µVRMS
90µVRMS
Speed Limitations
To avoid op amp slew rate limiting at maximum clock
frequencies, the signal amplitude should be kept below a
specified level as shown in Table 9.
Clock Feedthrough
Clock feedthrough is defined as the RMS value of the clock
frequency and its harmonics that are present at the filter’s
output pin (9). The clock feedthrough is tested with the
input pin (2) grounded and depends on PC board layout
Table 9. Maximum VIN
INPUT FREQUENCY
≥250kHz
≥700kHz
MAXIMUM VIN
0.50VRMS
0.25VRMS
11
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