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LTC1646CGN View Datasheet(PDF) - Linear Technology

Part Name
Description
Manufacturer
LTC1646CGN
Linear
Linear Technology 
LTC1646CGN Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
LTC1646
APPLICATIO S I FOR ATIO
Since there is no bulk capacitance to damp the parasitic
trace inductance, supply voltage transients excite para-
sitic resonant circuits formed by the power MOSFET
capacitance and the combined parasitic inductance from
the wiring harness, the backplane and the circuit board
traces. These ringing transients appear as a fast edge on
the 3.3V or 5V supply, exhibiting a peak overshoot to 2.5
times the steady-state value followed by a damped sinu-
soidal response whose duration and period is dependent
on the resonant circuit parameters. Since the absolute
maximum supply voltage of the LTC1646 is 7V, transient
protection against 3.3V and 5V supply voltage spikes and
ringing is highly recommended.
In these applications, there are two methods for eliminat-
ing these supply voltage transients: using Zener diodes to
clip the transient to a safe level and snubber networks.
Snubbers are RC networks whose time constants are
large enough to safely damp the inductance of the board’s
parasitic resonant circuits. As a starting point, the shunt
capacitors in these networks are chosen to be 10× to 100×
the power MOSFET’s COSS under bias. The value of the
series resistor (R6 and R7 in Figure 13) is then chosen to
be large enough to damp the resulting series R-L-C circuit
and typically ranges from 1to 10. Note that in all
LTC1646 circuit schematics, Zener diodes and snubber
networks have been added to each 3.3V and 5V supply rail
and should be used always. These protection networks
should be mounted very close to the LTC1646’s supply
voltage using short lead lengths to minimize lead induc-
tance. This is shown schematically in Figure 13 and a
recommended layout of the transient protection devices
around the LTC1646 is shown in Figure 14.
5VIN
LTC1646*
TZ1
TZ2
C2
VIAS TO
GND PLANE
C3
GND
3VIN
*ADDITIONAL DETAILS OMITTED FOR CLARITY
DRAWING IS NOT TO SCALE!
1646 F14
Figure 14. Recommended Layout for
Transient Protection Components
VIN1
5V
LONG 5V
VIN2
3.3V
LONG 3.3V
R6 2.7
R7 1.8
R1
0.005
Q2
IRF7413
R3
10
R2
0.007
Q1
IRF7413
5VOUT
AT 5A
3VOUT
AT 7.6A
R4
10
R5
1k
C1
0.01µF
Z1
C2
0.1µF
8
9
10
7
12
11
5
3VIN
3VSENSE GATE 3VOUT 5VIN
5VSENSE
5VOUT
LTC1646**
GND
Z1, Z2: BZX84C6V2
6
**ADDITIONAL DETAILS OMITTED FOR CLARITY
Figure 13. Place Transient Protection Device Close to the LTC1646
Z2
C3
0.1µF
1646 F13
17

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