LTC2273I View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTC2273I

16-Bit, 80Msps/65Msps Serial Output ADC

Linear Technology 

LTC2273/LTC2272

APPLICATIONS INFORMATION

CONVERTER OPERATION

The core of the LTC2273/LTC2272 are CMOS pipelined

multi-step converters with a front-end PGA. As shown

in Figure 1, the converter has five pipelined ADC stages.

A sampled analog input will result in a digitized value

nine clock cycles later (see the Timing Diagram section).

The analog input (AIN+, AIN–) is differential for improved

common mode noise immunity and to maximize the input

range. Additionally, the differential input drive will reduce

even order harmonics of the sample and hold circuit. The

encode clock input (ENC+, ENC–) is also differential for

improved common mode noise immunity.

Each pipelined stage shown in Figure 1 contains an ADC,

a reconstruction DAC, and an error residue amplifier. The

function of each stage is to produce a digital representation

of its input voltage along with the resulting analog error

residue. The ADC of each stage provides the quantization,

and the residue is produced by taking the difference between

the input voltage and the output of the reconstruction DAC.

The residue is amplified by the residue amplifier and passed

on to the next stage. The successive stages of the pipeline

operate on alternating phases of the clock so that when

odd stages are outputting their residue, the even stages

are acquiring that residue and vice versa.

The pipelined ADC of the LTC2273/LTC2272 has two phases

of operation determined by the state of the differential

ENC+/ENC– input pins. For brevity, the text will refer to

ENC+ greater than ENC– as ENC high and ENC+ less than

ENC– as ENC low.

When ENC is low, the analog input is sampled differentially

onto the input sample-and-hold capacitors, inside the “S/H

& PGA” block of Figure 1. On the rising edge of ENC, the

voltage on the sample capacitors is held. While ENC is

high, the held input voltage is buffered by the S/H amplifier

which drives the first pipelined ADC stage. The first stage

acquires the output of the S/H amplifier during the high

phase of ENC. On the falling edge of ENC, the first stage

produces its residue which is acquired by the second stage.

The process continues to the end of the pipeline.

Each ADC stage following the first has additional error

correction range to accommodate flash and amplifier offset

errors. Results from all of the ADC stages are digitally

delayed such that the results can be properly combined

in the correction logic before being encoded, serialized,

and sent to the output buffer.

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